lecture03

lecture03 - Simulation TestBench Introduction to Functional...

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1 Simulation & TestBench Introduction to Functional Verification Lecture 3 Review: Design Modeling ± Behavior model – functional model .. PIs POs black – limited timing information – describe I/O behavior ± Timing - given inputs, when outputs change . box clk a b c c=a+b+ab clk a b c
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2 Review: Design Models ± RTL Model – functional + timing + latches –c = a+b ± Structural RTL Model – functional + timing + latches + primitives tmp_a = latch(clk, a) tmp_b = latch(clk, b) c = tmp_a + tmp_b tmp_c = a + b c = latch(clk, tmp_c) – primitive: and, or, MUX, nmos, pmos, etc. = • ripple-carry adder • carry-look-ahead adder Sequential model combinational logic la adder c s a b L ± We need: functional model for combinational logic + a state transition tches clk reset s0 s1 ab a+b ab diagram –s = a b L – c = ab + aL + bL a+b # of states = 2^M How to represent all reachable states?
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3 Functional verification demand ± Functional verification cost grows faster than design complexity (cycles 100M 10B (cycles) 100K 1M 10M 1M (gates) A simple example of why ± If you have a design with 10-bit flipflops, the maximum number of states is 1024 ± If it is 11-bit, the number of states is 2048 ± So in theory, the verification space grows exponentially while the design grows linearly
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4 Resource spending ± Functional Verification ± Post-Silicon Validation Functional verification Post-silicon validation 1 st silicon 11 8 1 9 30 months Verification approaches ± Vector (test bench) Simulation – Define correctness – Test case generation – Coverage metric • Assertion-based properties – Hardware emulation ± Formal Verification – Logic Equivalent Checking • RTL to Gate, RTL to Schematics – Model checking ± “Semi-formal” Approach – Symbolic simulation – Effective for array verification
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5 Challenges in verification ± Specification – Correctness may not be well-defined – This is especially true at unit level ± Size and Complexity – Vector simulation remains the only effective way for full-chip functional verification – Model checking remains limited – Symbolic simulation remains limited ± Verification re-use ± Quality Concerns – Never enough – Depends on experience and time-to-market Verification relies on simulation ± Full-chip functional verification relies on vector simulation – Formal method is not powerful enough yet ± Test vectors (testbench) are prepared in a semi-random fashion – To test an adder: – ( normal flow ) supply random numbers –( boundary conditions ) also make sure to supply the maximum and minimum numbers • to test the carry output
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6 Level of simulation ± RTL – low complexity – verify function – zero delay model ± Gate – zero/unit delay model – fault injection and simulation ± Transistor – unit switching delay model – transistor strengths/sizes included – verify custom circuit designs Verification by simulation Simulation program Results Stimuli & control – Checking for error conditions (bus contention) – Ability to change delays to test worst-case timing
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  • Fall '08
  • Staff
  • formal methods, Electronic design automation, Functional Verification, Functional Verification Lecture, Functional verification cost

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lecture03 - Simulation TestBench Introduction to Functional...

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