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hw3 - ECE156A,Fall2008 VHDL&SynthesisHomework#3...

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ECE 156A, Fall 2008 VHDL & Synthesis Homework #3 DUE: Start of Class, Wednesday, October 28 th NOTE: For This assignment we will run your code through a test bench so you need to name your modules as specified below. If your code cannot be simulated it will result in loss of points. You can name lower level modules whatever you like, but the top level must be written exactly as stated. For example if this was your module prototype: module name(out, in1, in2, in3). You need to keep it the module name the same as well as the argument (input/output) ordering. Part I: Using any of the modules from HW#1 and any new modules, create an 8 x 4 bit register file. This register file will have a 4‐bit input(d_in) and 4 bit output(d_out), a 3‐bit address(a_in), write enable(we), clock(clk), and asynchronous reset signal (a_reset). (Hint: this should be easy if you use components from the previous assignment). If (we) is set high then d_in will be written to the register selected by address (a_in). Data out(d_out) will always display the value of the register selected by address(a_in).
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