hw3 - ECE
156A,
Fall
2008


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Unformatted text preview: ECE
156A,
Fall
2008
 VHDL
&
Synthesis
Homework
#3
 
 DUE:
Start
of
Class,
Wednesday,
October
28th

 
 NOTE:
 For
This
assignment
we
will
run
your
code
through
a
test
bench
so
you
need
to
name
 your
modules
as
specified
below.
If
your
code
cannot
be
simulated
it
will
result
in
loss
of
points.
 You
can
name
lower
level
modules
whatever
you
like,
but
the
top
level
must
be
written
exactly
 as
stated.
For
example
if
this
was
your
module
prototype:
module
name(out,
in1,
in2,
in3).
You
 need
to
keep
it
the
module
name
the
same
as
well
as
the
argument
(input/output)
ordering.
 
 Part
I:

 Using
any
of
the
modules
from
HW#1
and
any
new
modules,
create
an
8
x
4
bit
register
 file.
This
register
file
will
have
a
4‐bit
input(d_in)
and
4
bit
output(d_out),
a
3‐bit
address(a_in),
 write
enable(we),
clock(clk),
and
asynchronous
reset
signal
(a_reset).
(Hint:
this
should
be
easy
 if
you
use
components
from
the
previous
assignment).
If
(we)
is
set
high
then
d_in
will
be
 written
to
the
register
selected
by
address
(a_in).
Data
out(d_out)
will
always
display
the
value
 of
the
register
selected
by
address(a_in).
 

 module
regfile(d_out,
d_in,
a_in,
a_reset,
we,
clk);
(note
din
and
dout
must
be
4
bits
wide)
 
 Part
II:

 Using
the
D
Flip‐Flop
module
from
HW#1
design
a
4‐bit
counter.
When
enable
is
high,
 the
counter
counts,
otherwise
the
count
is
held
the
current
value.
Additionally,
there
are
two
 reset
signals,
synchronous
(reset)
and
asynchronous
(a_reset),
and
the
clock
signal
(clk).
Both
 resets
should
be
active
low.
The
Verilog
code
should
be
written
in
“structural
mode,”
not
 “behavioral.”
That
is,
you
should
use
the
D
Flip‐Flop
components
of
HW#1
and
connect
them
 with
the
primitive
gates
(AND,
OR,
NOT
…)
from
Verilog
to
create
this
counter.
Use
this
 prototype
for
your
D
Flip‐Flop:
 
 module

dff(q,
q_bar,
d,
a_reset,
reset,
enable,
clk);

(same
as
HW
#2)
 
 a).
First,
design
the
4‐bit
counter
so
that
it
counts
up
from
0
to
15
and
repeats.

 
 module
upcnt(count,
start,
a_reset,
s_reset,
clk);
(note
count
must
be
4
bit
output)
 
 b).
Second,
make
a
modified
version
of
the
4‐bit
counter
that
will
count
down
from
6
to
0
and
 repeats.

 
 module
dwncnt(count,
start,
a_reset,
s_reset,
clk);
(note
count
must
be
4
bit
output)
 
 
 Part
III:

 Create
a
logic
block
so
that
a
4‐bit
number
is
displayed
on
a
standard
7
segment
display.
 Remember,
for
a
standard
7
segment
display,
the
7
signals
(a,
b,
c,
d,
e,
f,
and
g)
need
to
be
set
 to
“ZERO”
to
drive
current
into
the
display
(active
low).
The
number
shown
in
the
7segment
 display
should
be
encoded
into
hexadecimal,
that
is,
numbers
from
10
to
15
need
to
be
shown
 as
A,
B,
C,
D,
E
and
F.
For
letters
B
and
D,
decode
them
so
that
they
appear
as
lowercase
“b”
 and
“d”
etc.
This
block
should
be
as
small
as
possible,
so
minimize
the
equations.
The
output
of
 this
block
corresponds
to
each
of
the
LEDs
in
the
display
as
follows:
 
 module
bcdto7(a,
b,
c,
d,
e,
f,
g,
all_out,
d_in);
(note
d_in
must
be4
bits
wide
and
all_out
must
 be
7
bits
wide)
 
 
 
 The
signal
all_out
should
output
all
of
the
outputs
as
a
7‐bit
value.
You
must
put
this
signal
on
 your
waveforms
displaying
the
value
in
hexadecimal.
The
encoding
should
be
as
follows:
 all_out[0]
=
a
 all_out[1]
=
b
 all_out[2]
=
c
 all_out[3]
=
d
 all_out[4]
=
e
 all_out[5]
=
f
 all_out[6]
=
g
 
 
 Turn‐In
Directions:


 Please
print
your
Verilog
code
(Modules
and
Testbenches)
and
any
results
generated
by
 the
simulator
(waveforms
etc.)
Write
comments
on
the
code
and
Waveform
simulation
to
 explain
them.
A
write‐up
(about
1
page)
should
be
attached
to
the
Verilog
code
answering
all
 questions
asked
in
this
assignment,
and
any
hardships
noted.
Please
send
an
email
that
includes
 your
Verilog
files
to
the
TA.

 
 Brendon
Bolin(bbolin@gmail.com)
 
 E‐Mail
Format:
 Subject:

ECE156A
HW#2,
<your
name>
 Content:
 1.
Your
student
ID
 2.
Your
name
 3.
All
of
your
Verilog
files
clearly
named
in
a
tar
or
zip
file.
 
 Questions?
 If
you
have
any
confusion
about
what
the
questions
are
asking,
please
E‐Mail
the
TA
or
make
 a
post
on
the
course
Google
group.
Don’t
wait
until
the
last
minute
to
start
this
assignment,
as
 it
is
more
complicated
than
HW
#2.
Also,
make
sure
every
module
from
HW#2
works
correctly
 before
you
attempt
to
do
HW#3.
Good
Luck!
 ...
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