hw5 - ECE 156A Fall 2009 VHDL& Synthesis...

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Unformatted text preview: ECE 156A Fall 2009 VHDL & Synthesis Homework #5 DUE: December 7th. Part I: Design of a Simple Processor For this assignment your task will be to design a piece of hardware that will perform some of the functionalities of a simple processor. This hardware may include several pieces from your past homework. The main components of this processor will be a state machine, a small control unit and a memory unit. However, one peculiarity of this processor is that all the instructions and operands will be given bit by bit to a shift register, which is part of the control unit. The descriptions of each of the units are given as follows: The state machine: Reset state: Initializes the FSM (finite state machine) and generates the "reset" signal to the control unit. Run/Idle state: The operations given to the control unit are executed only in this state, which is indicated by the "run" signal. Shift state: When the FSM reaches this state, the control unit starts to shift the instructions/operands to be executed from the input "data_in." Update: In this state, the contents of the shift register (the instructions) are latched onto another set of latches ("shadow" register), so that the instructions/operands are already "stabilized" when executed. The contents are latched by the "update" signal. A possible HDL description of the state machine is given as follows: module fsm (clk, x, rs, reset, shift, update, run); `define RS 4'b0001 // Reset state `define RI 4'b0010 // Run/Idle state `define SH 4'b0100 // Shift state `define UP 4'b1000 // Update state input clk; input x; // signal that makes the FSM change state input rs;// signal that initializes the FSM to RS output reset, shift, update, run; reg [3:0] state, next_state; ... endmodule The control and memory units: These two devices can be placed together and will be working based on the outputs of the state machine (reset, shift, update, run). When "reset" is activated, the memory unit and the internal registers are reset. At the "shift" state, data from "data_in" is shifted into the shift register. At "update," this content is latched onto the "shadow" registers. And finally during "run", the stable contents of the shadow register tell the control unit or memory unit what to do. The size of the memory unit will be set to four 4 ­bit words, giving an address of 2 bits. Each instruction is a 8 ­bit word. The meaning of each bit is described below. The information (8 bits) for the control unit/memory is set up as follows: Bits 7:6: Opcode: 00 -Initialize the MEM: writing data to the MEM before they can be used. 01 -Arithmetic operation. 10 -Logic operation. 11 -Buffering data: send input data to output. Bits 5:4: Will be the address of the Mem when the opcode is 00. When opcode is 01, bit 5 will set the addition(0) or subtraction(1) operations. When opcode is 10, bit 5 will set the AND(0) or OR(1) operations. Bits 3:0: Will be the data to be written to the Mem when the opcode is 00. When opcode is 01 or 10, bits 3:2 and bits 1:0 will be the addresses of the operands. Bits 4:0: Will be the data to be sent to the output when the opcode is 11 (Buffer operation). A possible interface of this control unit described in Verilog is as follows: module control_unit (clk, data_in, reset, run, shift, update, data_out, z); // Define the codes for the operations: `define INITLZ_MEM 2'b00 `define ARITH 2'b01 `define LOGIC 2'b10 `define BUFFER 2'b11 // I/O definitions: input clk, data_in; // The clock and the serial input. input reset, run, shift, update; // Signals from the FSM output data_out; // Data shifted out bit by bit. This is the //output of the shift register. output [4:0] z; // Internal memory: reg [3:0] mem [3:0]; // Variables for the internal shift register and the shadow_reg: // bits [7:6] = opcode (INITLZ_MEM, ARITH, LOGIC, BUFFER) // bits [5:4] = address in the memory when opcode=INITLZ_MEM // 0/1 for addition/subtraction when opcode=ARITH // 0/1 for AND/OR when opcode=LOGIC // bits [3:0] = data to the mem when opcode = INITLZ_MEM // = the addresses of the data in the mem when opcode = ARITH // or LOGIC // bits [4:0] = data sent out to the output when opcode = BUFFER reg [7:0] shift_reg, shadow_reg; // Extra variable definitions: wire data_out; reg [4:0] z; reg [1:0] address; reg [1:0] addressA, addressB; ... endmodule Suggestions: 1. Write separate HDL descriptions for the FSM and the control unit and connect them using a top ­level file. 2. Notice that the FSM is a Moore ­type of state machine. 3. To avoid some race conditions, you may need to make the FSM and the control unit running at different clocks. 4. Also notice that the memory unit is just an array of registers. 5. And finally, you may write your descriptions in behavioral model. It's may be easier. Part II: Design Compiler This exercise is to practice the synthesis process from RTL code to the gate level simulation. It involves writing and simulating RTL code, synthesizing your code with the Design Compiler, and simulating the output of DC. Part a) Write a counter that counts from 0 to 10 in RTL (Verilog). Your counter should have an asynchronous reset signal to reset the counter to 0 when reset is 1, an enable signal to allow counting when enable is 1 and to hold the current count when enable is 0, and a clock signal (count increments only during the positive edge of the clock). The only output is the current count. Write a complete test bench that exercises the boundary conditions and normal operation of the counter. Part b) Synthesize your RTL code with the Design Compiler. Generate a gate ­level Verilog version of your counter. (Note you may have to make changes to part a to allow your code to be synthesized.) Part c) Simulate your DC ­generated gate ­level code and try to prove that the gate level and RTL behave the same. You will need to include in your Modelsim project class.v, available on the google groups webpage. Design Compiler Turn in: • Verilog RTL code for the counter and test bench WITH COMMENTED CODE • Waveform of RTL simulation WITH COMMENTED WAVEFORM • DC ­generated gate ­level Verilog code • DC ­generated output report (area report) • Waveform of gate ­level simulation/verification Simple Processor Turn in: Simulate your design at least once for all the instructions and write comments throughout your code and simulation waveforms. Include a 1 ­page report explaining each instruction and how you implemented it; also explain any difficulties you had. E ­mail your code to the TA, and submit a hardcopy in class or in lab by the due date. E ­mail to TA: Brendon ([email protected]) E ­Mail Format: Subject: ECE156A HW#5, <your name> Content: 1. Your student ID 2. Your name 3. All of your Verilog files clearly named in a tar or zip file. ...
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This note was uploaded on 05/20/2010 for the course ECE 156a taught by Professor Staff during the Fall '08 term at UCSB.

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