hw4 - ECE 156A, Fall 2009 VHDL & Synthesis...

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Unformatted text preview: ECE 156A, Fall 2009 VHDL & Synthesis Homework #4 DUE: In Class, Monday, November 23rd. NOTE: The purpose of this assignment is to understand the essence of design verification, a very crucial step in hardware design. This homework requires you to think a little bit harder. There is no absolutely correct answer for this homework. You need to be creative in your verification methodology. Problem 1: From HW #3, everyone should have a gate level implementation of their designs. For this assignment you will implement your HW #3 up counter and BCD to seven segment decoder modules using only behavioral constructs such as, always, if ­then ­else, =, etc. Please do not use “assign” to produce equivalent gate structures in your behavior model. Connect the “up counter” to the “seven segment decoder” so that the counters output can be displayed on a seven segment display. Now take your two designs, one at gate ­level and one at behavioral level, and use Verilog simulator to prove that they behave functionally the same. You should construct a miter with the behavioral and gate level versions of each module to test functional equivalence. For this assignment the miter is essentially a 4 ­input, 1 output circuit. For both designs you apply the same inputs, and pair ­wise XOR the outputs, finally you and feed everything into huge OR gate. If the two copies of the design are equivalent, then regardless of what inputs you supply, and in what order and time, the miter output will never produce a 1. It is important to note that prior to testing the flip ­flops in the two circuit copies must have the same initial state. This is the definition of strong sequential design equivalence. Gate Level Behavioral Please note that this 4 input miter is a sequential circuit. Hence, simply exhaustively trying all the 2 = 16 combinations of input assignments without considering the timing sequence and the initial state, does not guarantee there is not a way to make the output = 1. Your job is the following: 1. Produce two copies of the up counter and the BCD to seven ­segment decoder, one at gate ­level (From HW #3) and the other at behavior level. 2. Construct a miter module as described above, for the counter connected to the seven segment decoder circuit. 3. Develop a verification methodology and its associated testbench(s) in order to prove that your miter will, under any input condition, never output a 1. This is the part requiring your creativity. Problem 2: Write and simulate a Verilog description of a module that will watch a synchronous serial input and detect the pattern 0100. Assume that the data is stable at the falling edge of the clock and that the rightmost ­bit in this pattern arrives first. Also assume that the reset signal is active ­low. Module should be declared as: module machine_x(z, clk, in, reset); input clk, in, reset; output z; Where x is a for part a and b for part b. Part a) Develop a state transition graph and implement the module as a state machine. The simulation results should show all the possible state transitions. Write comments in your code and on the simulation waveform. Also, include the state diagram. Part b) Implement the module using a shift register. Using a miter like in problem 1, show that machine_a and machine_b are equivalent in their input/output behavior. Verifying each module individually before combining them with the miter may help if you are having problems. Turn ­In Directions: Please print your Verilog code (Modules and Testbenches) and any results generated by the simulator (waveforms etc.) Write comments on the code and Waveform simulation to explain them. A write ­up (about 1 page) should be attached to the Verilog code explaining any 4 hardships encountered, your testing methodology and any other comments about the assignment. Please send an email that includes your Verilog files the TA. Brendon ([email protected]) E ­Mail Format: Subject: ECE156A HW#4, <your name> Content: 1. Your student ID 2. Your name 3. All of your Verilog files clearly named in a tar or zip file. Questions? If you have any confusion about what the questions are asking, please E ­Mail the TA immediately. Don’t wait until the last minute to start this assignment, as it is more complicated than HW #3. Also, make sure every module from HW#3 works properly before you attempt to do HW#4. Good Luck! ...
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This note was uploaded on 05/20/2010 for the course ECE 156a taught by Professor Staff during the Fall '08 term at UCSB.

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