hw2 - ECE
156A
–
Fall,
2009


Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ECE
156A
–
Fall,
2009
 Homework
#2:
VHDL
&
Synthesis
 DUE:
In
Class,
Monday,
October
19th
 
 
 
 The
purpose
of
this
homework
assignment
is
to
get
you
familiar
with
the
Verilog
 simulation
tool
you
will
be
using.
The
default
tool
is
Modelsim.
However,
using
other
tools
is
 perfectly
ok.
The
key
is
that
you
need
to
know
how
to
use
the
tool
to
design
hardware
in
 Verilog
and
also
be
able
to
simulate
the
design
to
verify
its
correctness.
Hw2.zip
contains
 templates
for
each
of
the
Verilog
modules
to
be
created.
You
are
free
to
create
test
benches
 how
you
see
fit,
however
they
must
adequately
test
the
module.
 
 a)
Understand
the
basic
features
of
the
logic
simulator
software.
According
to
what
you
learn
 about
the
software
of
your
choice,
describe
the
major
steps
of
putting
together
a
design
using
 this
software.
What
major
components
are
involved?
If
you
are
using
other
tools,
please
specify
 the
tool
name
and
sources.

 
 b)
Use
ONLY
the
Verilog
gate‐level
primitives
(AND,
OR,
NOT,
NAND,
NOR,
XOR)
to
design
and
 simulate
an
“8
to
1
MUX.”

 
 c)
Again,
using
ONLY
the
Verilog
gate‐level
primitives
(AND,
OR,
NOT,
NAND,
NOR,
XOR)
to
 design
and
simulate
a
“3
to
8
Decoder.”

 
 d)
Again,
using
ONLY
the
Verilog
gate‐level
primitives
(AND,
OR,
NOT,
NAND,
NOR,
XOR)
to
 design
and
simulate
an
“8
to
3
Encoder.”
Use
the
previous
module
(Decoder)
in
the
simulation
 testbench
to
verify
correctness.
Explain
this
process
in
the
write‐up.

 
 e)
Similarly,
using
ONLY
the
Verilog
gate‐level
primitives
design
and
simulate
a
single
D
FlipFlop
 with
the
following
features:

 • Has
an
asynchronous
reset
signal
(ARESET)
and
a
synchronous
reset
signal
(RESET),
which
 both
need
to
be
active
LOW,
that
is,
if
the
signal
is
zero,
then
the
flip‐flop
is
reset
to
zero.

 • Has
an
enable
signal
(ENABLE),
which
is
active
low.

 • Has
Q
and
Qbar
output
signals.

 
 f)
Similarly,
using
ONLY
the
Verilog
gate‐level
primitives
and
the
D
FlipFlop
from
the
previous
 step,
design
and
simulate
a
single
JK
FlipFlop
with
the
following
features:
(You
MUST
use
the
 DFF
module
from
the
previous
step)

 • Has
an
asynchronous
reset
signal
(ARESET)
and
a
synchronous
reset
signal
(RESET),
which
 both
need
to
be
active
LOW,
that
is,
if
the
signal
is
zero,
then
the
flip‐flop
is
reset
to
zero.

 • Has
an
enable
signal
(ENABLE),
which
is
active
low.

 • Has
Q
and
Qbar
output
signals.

 
 You
should
NOT
use
behavioral
statements
like
“assign”
in
this
homework.
 
 Turn‐In
Directions:


 Please
print
your
Verilog
code
(Modules
and
Testbenches).
Write
comments
in
the
code
 where
applicable
to
ensure
the
code
clear.
Simulation
waveforms
need
to
be
printed
and
 submitted.
Students
turning
in
poor
waveforms
will
be
asked
to
make
corrections
and
resubmit
 them.
 
 The
waveforms
must
meet
the
following
criteria
in
order
to
receive
full
credit.

 • The
waveforms
must
be
commented
showing
and
describing
the
areas
of
interest.

 • Background
must
not
be
black.
 • Signals
of
more
than
1‐bit
should
be
displayed
asa
bus
in
binary
or
hex.
 
 A
write‐up
of
about
one
page
should
be
attached
to
the
Verilog
code
answering
all
 questions
asked
in
this
assignment,
and
any
hardships
noted.
Email
the
source
Verilog
to
 brendon2k@gmail.com.
All
of
the
source
files
should
retain
the
original
name
and
all
of
the
 modules
should
retain
the
prototype
as
contained
in
hw2.zip.


 
 ...
View Full Document

This note was uploaded on 05/20/2010 for the course ECE 156a taught by Professor Staff during the Fall '08 term at UCSB.

Ask a homework question - tutors are online