30 - EE200 DIGITAL LOGIC CIRCUIT DESIGN Class Notes CLASS...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
EE200(class 15-1) Prof. M.M. Dawoud 141 EE200 DIGITAL LOGIC CIRCUIT DESIGN Class Notes CLASS 15-1 The material covered in this class will be as follows: Synchronous counters. ± Binary counter. ± Up-down counter. ± BCD counter. ± Binary counter with parallel load. Synchronous Counters Synchronous counters can be designed using the design procedure of the clocked sequential circuits. The count pulses are applied to the clock inputs of all flip-flops of the counter. Therefore the changes in the outputs occur at the same time. Several typical synchronous counters are presented in this section and their operation explained. Synchronous binary counter The operation of the synchronous binary counter is so simple and follows an easy complementing pattern that a simple design procedure can be followed. There is no need to follow the general procedure for the design of synchronous sequential circuits. If we inspect the count cycle or the timing diagram of the binary counter we find the following: 1. A 0 complements every time the count pulses go from 1 to 0.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/21/2010 for the course EE EE200 taught by Professor Prof.ahmed during the Spring '09 term at King Fahd University of Petroleum & Minerals.

Page1 / 3

30 - EE200 DIGITAL LOGIC CIRCUIT DESIGN Class Notes CLASS...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online