26 - EE200 DIGITAL LOGIC CIRCUIT DESIGN Class Notes CLASS...

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EE200(class 13-1) Prof. M.M. Dawoud 119 EE200 DIGITAL LOGIC CIRCUIT DESIGN Class Notes CLASS 13-1 The material covered in this class will be as follows: State reduction. State assignment. Design procedure. Flip-flop excitation tables. State reduction In the design of sequential circuits, we need to reduce the number of flip flops and the number of logic gates used in the combinational circuit part. Reduction of the number of flip-flops may result from the reduction of the number of states in the circuit. This is possible if we are interested in the input output relationship of the circuit and not in the outputs of the flip-flops. The state reduction procedure will be illustrated with an example. Consider the given state diagram 0/0 a c b e 1/1 1/0 d f g 0/0 0/0 0/0 1/0 1/0 0/0 1/1 1/1 0/0 1/1 0/0
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EE200(class 13-1) Prof. M.M. Dawoud 120 Suppose that the input sequence to the circuit is 01010110100 starting from the initial state a. Then the output and next state will be as follows: State a a b c d e f f g f g a Input
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26 - EE200 DIGITAL LOGIC CIRCUIT DESIGN Class Notes CLASS...

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