EE200(class 113)
Prof. M.M. Dawoud
109
EE200 DIGITAL LOGIC CIRCUIT DESIGN
Class Notes
CLASS 113
The material covered in this class will be as follows:
⇒
Positive edge triggered D flipflop.
⇒
Characteristic tables.
⇒
JK and T flipflops.
⇒
Direct inputs.
⇒
Analysis of clocked sequential circuits.
Positive Edge triggered D FlipFlop
The positive edge triggered D flipflop consists of three basic SR
latches. This arrangement is shown in the logic diagram.
When CLK=0 and D=0, then the outputs of gates 1, 2, 3, and 4 are
going to be 0111. If D=1 while CLK=0, then the outputs of these
gates are going to be 1110 instead. In both cases, S=R=1, which
make Q and Q’ are 01 or 10. i.e. one of the two stable states.
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View Full DocumentEE200(class 113)
Prof. M.M. Dawoud
110
DJ
QK
Q
′
′
=
+
1
t
QJ
Q
K
Q
+
′
′
=+
Suppose that CLK becomes 1 while D=0. The output of gate 3
(which is R) becomes 0. this will reset the output flipflop. Once R
is 0, then D can change to 1
and R remains 0. This means that Q
remains 0 while CLK is 1. No change will occur to Q until the clock
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 Spring '09
 prof.ahmed
 Logic gate, 1 qt, Prof. M.M. Dawoud, 0 0 1 1 K, 0 1 0 1 Qt, 0 1 Qt

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