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Unformatted text preview: indicating the parity bit column giving 1 to the parity bit for the states which are not included in the BCD. Let the parity bit represent the error-detection function. Design a combinational circuit for the error detection. 4-We have a decoder with three inputs, a, b, and c and eight active low outputs, labeled 0 through 7. In addition, there is an active low enable input EN . We wish to implement the following function using the decoder and as few NAND gates as possible. Show the block diagram ∑ = ) 15 , 9 , 7 , 3 , 1 ( ) , , , ( m e c b a f...
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- Spring '09
- Electrical Engineering