nature06458-s1 - Silicon Nanowires as Highly Efficient...

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Unformatted text preview: Silicon Nanowires as Highly Efficient Thermoelectric Materials ― Supplementary Information (Experiment) Akram I. Boukai#, Yuri Bunimovich#, Jamil Tahir-Kheli, Jen-Kan Yu, William A. Goddard III, and James R. Heath* Device Fabrication and Measurement Setup The devices used in this report were fabricated from intrinsic silicon-on-insulator (SOI) substrates (Ibis Technology) with a buried oxide thickness of 150nm. The top Si(100) epilayer began with a thickness of 400nm and was thinned through repeated thermal oxidations and wet chemical etching steps until the desired Si layer thickness (20nm or 35nm) was obtained. AFM analysis revealed a smooth surface with an rms roughness of ~3.6 Å. Next, the Si epilayer was doped using a boron containing spin-on dopant (Filmtronics Boron-A) (21). After spin coating, the substrates were baked (250 ºC; 5 min) and annealed under flowing N 2 using a rapid thermal processor at temperatures corresponding to the desired doping concentration by allowing the boron to diffuse into the silicon. Four-point probe conductivity measurements determined the p-type doping concentration. We have previously reported that the doping profile through the thickness of the epilayer drops rapidly from the top surface (Figure S1). 5 3 1 Dopant Concentration (x10 19 cm-3 ) 31 27 23 19 Si epilayer thickness (nm) 35 5 3 1 Dopant Concentration (x10 19 cm-3 ) 31 27 23 19 Si epilayer thickness (nm) 35 Figure S1. P-type dopant profile through the Si epilayer of an SOI substrate from which the NWs were fabricated. The profile was measured by repeated cycles of 4-point conductivity measurements of the film and dry etching to thin the film. After the diffusion doping process, the substrates were used to fabricate Si NWs using the SNAP process (20). The depth of the NWs was nominally 20nm (the SOI substrate thickness). However, the “electrical” depth, the distance at which the doping concentration decreased by an order of magnitude or more, was 10-15 nm (Fig. S1). SEM and AFM were used to determine the SUPPLEMENTARY INFORMATION doi: 10.1038/nature0 6 4 58 1 dimensions of our Si NWs. Devices contained from 10 to 400 NWs connected in parallel. For all measurements on the 10 nm wide wires other than thermal conductivity, monolithic contacts were used in order to minimize the contact resistance (Fig S2.). The use of monolithic contacts means that the NWs constitute a bridge between two micrometer-sized pads, with the NWs and pads all part of the same single crystal silicon structure. This method effectively removes contact resistance. Figure S2. The approach for minimizing contact resistance to NW arrays. A. Drawing of the single crystal structure consisting of contact pads bridged by NWs. B. Scanning electron micrograph of an array of about a dozen 17 nm wide Si NWs contacted by a 0.4 micrometer wide bar of Si. Metal contacts are made to the bar, rather than to the NWs....
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This note was uploaded on 05/21/2010 for the course MS Thermoelec taught by Professor Snyder during the Spring '10 term at Caltech.

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nature06458-s1 - Silicon Nanowires as Highly Efficient...

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