week8_friday - CSCC 69H3 Operating Systems Spring 2010...

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Unformatted text preview: CSCC 69H3 Operating Systems Spring 2010 Professor Bianca Schroeder U of T Paging We can fit Process D into memory, even though we dont have 3 contiguous frames available! A.0 A.1 A.2 C.0 C.1 0 1 2 3 4 5 6 7 8 Main memory A.0 A.1 A.2 D.0 D.1 C.0 C.1 D.2 0 1 2 3 4 5 6 7 8 Main memory Suppose a new process, D, arrives needing 3 frames of memory Address translation Uses symbolic addresses (variable names) Uses logical addresses (relative to start of stack frame) Logical addresses need to be translated to physical addresses How does address translation work for Static/dynamic partitioning? Paging? int main() { int y; y = random(); printf(%d,y); } Compile Program binary Load & Execute Stack Code Data Heap Source code Process Stack Code Data Heap Memory 0x00000000 0x7FFFFFFF Support for Paging Operating system maintains page table for each process Page table records which physical frame holds each page virtual addresses are now page number + page offset page number = ? =vaddr / page_size page offset = ? vaddr % page_size Simple to calculate if page size is power-of-2 0 1 2 Process D consisting of 3 pages Page size is 8 bytes A.0 A.1 A.2 D.0 D.1 C.0 C.1 D.2 0 1 2 3 4 5 6 7 8 Main memory Page number 0 3 Page# Frame# 1 4 2 7 Page table Physical Address Virtual Address Page Lookups Overview Page number Page frame Offset Physical Memory Offset PTE Whats wrong with this approach? Need 2 references for address lookup (first page table, then actual memory) Idea: Use hardware cache of page table entries Translation Lookaside Buffer (TLB) Small hardware cache of recently used translations Page table Physical Address Virtual Address Page Lookups Overview Page number Page frame Offset Physical Memory Offset PTE Whats wrong with this approach? Need 2 references for address lookup (first page table, then actual memory) Idea: Use hardware cache of page table entries Translation Lookaside Buffer (TLB) Small, fully-associative hardware cache of recently used translations PTE (in Memory) Translation Lookaside Buffer (in hardware cache) TLB hit TLB miss Managing TLBs Who places translations into the TLB (loads the TLB)? Hardware (Memory Management Unit) Knows where page tables are in main memory OS maintains tables, HW accesses them directly Tables have to be in HW-defined format (inflexible) Software loaded TLB (OS) TLB faults to the OS, OS finds appropriate PTE, loads it in TLB Must be fast (but still 20-200 cycles) CPU ISA has instructions for manipulating TLB Tables can be in any format convenient for OS (flexible) Managing TLBs (2) OS ensures that TLB and page tables are consistent When it changes the protection bits of a PTE, it needs to invalidate the PTE if it is in the TLB Reload TLB on a process context switch Invalidate all entries Why? What is one way to fix it?...
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This note was uploaded on 05/22/2010 for the course CS CSCC69 taught by Professor Bianca during the Spring '10 term at University of Toronto- Toronto.

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week8_friday - CSCC 69H3 Operating Systems Spring 2010...

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