Page-93

# Page-93 - vGS 1 vGS 2 vGS 3 vGS 4 = v1 = 0 < Vt = v2 vDS 1...

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v GS 1 = v 1 = 0 < ¯ V t M1 is OFF i D 1 = 0 v GS 2 = v 2 v DS 1 = v DS 1 M2 is ? v GS 3 = v 1 V DD = V DD < ¯ V t M3 is ON v GS 4 = v 2 V DD = V DD < ¯ V t M4 is ON Since i D 1 = 0, by KCLs in no. 2 above , i D 2 = i D 1 = 0 and i D 3 + i D 4 = i D 1 = 0. Since i D 0 for both PMOS and NMOS, the last equation can be only satisfied if i D 3 = i D 4 = 0. We add the value of i D to the table above and look for transistors that are ON and have i D = 0. These transistors have to be in Triode region with v DS = 0. v GS 1 = v 1 = 0 < ¯ V t M1 is OFF i D 1 = 0 v GS 2 = v 2 v DS 1 = v DS 1 M2 is ? i D 2 = 0 v GS 3 = v 1 V DD = V DD < ¯ V t M3 is ON i D 3 = 0 v DS 3 = 0 v GS 4 = v 2 V DD = V DD < ¯ V t M4 is ON i D 4 = 0 v DS 4 = 0 Finally, from KVLs in no. 3. above, we have v o = V DD + v DS 3 = V DD . So, when both inputs are low, the output is HIGH. If needed, we can go back and find the state of M2. Assume M2 is ON. This requires v GS 2 > ¯ V t . Since i D 2 = 0 and M2 is ON, v DS 2 = 0 (M2 in Triode). From KVLs in no. 3.
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