This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: CS 151 Digital Logic Design, Fall Quarter 2009 CS 151
Midterm Name : , (Last Name) (First Name)
Student ID :
Signature : Instructions:
1. Please verify that your paper contains 14 pages including this cover. 2. Write down your StudentId on the top of each page of this quiz. 3. This exam is closed book. No notes or other materials are permitted.
4. Total credits of this midterm are 100 points. 5. To receive credit you must show your work clearly. 6. For possible regrade request make sure that your write clearly. 7. Calculators are NQT allowed. CS 151 Digital Logic Design, Fall Quarter 2009 Q1 [MUX/Decoder Application] [20 points] (a) Draw a black box of 15to1 multiplexer showing inputs, select signals and output.
How many select signals are required? [3 points] (b) Draw an implementation of the above ‘iSto—t line multiplexer using with two 8—to—t
line multiplexers. interconnect the two multiplexers appropriately. Each such
multiplexer would have three select signals. Label the select signals of one
multiplexer to be {a2, at, a0} and that of the other as {b2, lot, b0} (a0 and tea are
respective least significant select signals) [7 points] , . " .i‘éﬁ
M“ .i ,
7 a
i 7 t i ,
ts «mrwm"“'““”w ““ “ ”t mi?
:39 m“ “a ”My; CS 151 Digital Logic Design, Fall Quarter 2009 (0) Draw the truth table of {a2,a‘l,a0} and {b2,b1,b0} with the
15to1 as inputs [4 points] 5 a
/ ‘,.. ,
”a "F 3 W“ 3 ’ 3 f a ’ ,1 r ) (
‘5». 3. ,5. :3 l “*3: U‘ a U r: {"1 ““ a V17
* é a a 5‘ l » e
i» ‘1 a" , \ i “j "a a“; 5"; ("a r“
v} (:1. n 3 ‘9} ‘ K)“ x»; \e ‘2'] w I ,_ L f “at y A
{My 3 N! S  s a;
x w’ 3 x, 2 , 1
{5.3 1 , E ,A g a g ; L. 1 \ w .w
3, _ 3 a. ,_ ’1; m“
‘ 5‘ " ' 3‘ J
W" E iv: 3 ”3 ..
‘7 .
i
‘ “‘2 ’7‘
1 a 3 a! ‘W,’ l
t ‘4, 5
i . ¥ .
a f ,5: r g
~ ~, :1 g _/ v «H a
l i t st L5
a w i .’ 1
Z \ I]!
\ i ”I
l ‘ i;
”x, 1 e
a a»; 1. , \ f
4 ‘a w’
l r 1
E {"“l a Q l 1/ l
A, a l ,'
i ’ i,
i w.
a v x 5
, a g . r ‘ ‘ z 2
2 i 1, i g S ‘
‘ i i
4: i i i .‘m g
i ' ‘ ' 2 a} :
i 4 L" e 21 i i f l
" % E
5 ‘ ,
I 1 s \ ; l k
1 i a 3 ,. x 3 2
x a l . . K
‘u v t , I :
l i, j i
l x
3 i A7 3
V w , x
4 ‘ i 2
_ . N, V ~ . V ”LR V“ w M J, ,
l l
a a s r K
a i 1, t CH: '
1 select signals of the CS 151 Digital Logic Design, Fall Quarter 2009 (d) According to the truth table draw above, write down the Boolean expressions of a2,
a1, a0, b2, b1 and b0. Do NOT minimize the Boolean expressions [6 points] l i CS 151 Digital Logic Design, Fall Quarter 2009 Q2 [Sequential Logic] [25 points] A sequential circuit has one SR flipflop and one D flipflop, one input X. and one
output Y. The logic diagram of the circuit is shown in the following figure. Clock (a) Write clown the truth table of each of SR flipaflop and D flip—flop (showing input,
present state and output) [5 points] CS 151 Digital Logic Design, Fall Quarter 2009 (b) Write down the truth table of the above circuit showing input (X), present states (A, B), output (Y) and next states (An, Bn). Whenever needed, use labels Ap and Bp to
indicate previous states ofA and B respectively. [10 points] (c) Based on the above truth table, draw a finite state machine at the above circuit.
[1 O pomts} CS 151 Digital Logic Design, Fall Quarter 2009 QB [ALU design] [20 points] There is 4bit ALU with two inputs (A, B), input carry (Cm), select signals (81,80),
output (0) and carry out (Cour). The ALU performs following arithmetic operations m F=A+B(add) F=A+B+1
_ F= A (transfer) F= A + 1 (increment) ‘l F= A+ 8’ +1 (subtract) F= B’ (complement) F= B’+1 (negate)
1 (a) Draw a black box of ALU showing inputs and outputs. [5 points] CS 151 Digital Logic Design, Fall Quarter 2009 (b) lmplement the above ALU using multiplexers, only one 4bit adder and any other
logic gates components that you may need. [15 points] CS 151 Digital Logic Design, Fall Quarter 2009 Q4 [RTL Design] [35 points] There is an Encryption / Decryption engine that has three control inputs: k, e, d (each
of 1 bit), one 8bit data input I and one 8bit data output J. The engine works in the
following way: At any point of operation, if k = 1, the engine stores input data as a key.
Otherwise, if e = 1, the engine encrypts the input data using the previously stored key
and produces output data. On the other hand, if d = 1, the engine decrypts the input
data using the previously stored key and produces output data. If e and cl are both 1,
encryption has precedence over decryption. Assume that when the engine powers on
key is set to 0 (cleared). However, the engine will not encrypt or decrypt without
loading a valid key first after power on. if all inputs are 0 (Le, k = 0, e = 0, d = O), the
engine should be in an idle state without updating the output J or the sored key. in order to implement the above engine, you can use the followi'ig encryption/
decryption combination logic component (shown in the diagram below). The
combinational logic has two Bnbit inputs (DATA, KEY), a control input ENC, one 8—bit
output OUT. Depending upon the value of ENC, the combination circuit performs
either encryption or decryption of DATA using the KEY. lf ENC is 1, the output OUT =
encryption(DATA, KEY). lf ENC is 0, OUT = decryption(DATA, KEY). Use the following components: ‘3. Encrypt / Decrypt combination logic which behaves as described above. Encrypt I Decrypt 2. 8—bit positive clock edge triggered register, as shown below. The register is cleared
when CLR is 1. The register loads the input data when LD is 1 and CLR is 0. Input Register ( Output CS 151 Digital Logic Design, Fall Quarter 2009 (a) Draw an architectural template of the above system (CONTROLLER and
DATAPATH), showing all inputs and outputs [4 points] Mm V 10 CS 151 Digital Logic Design, Fall Quarter 2009 (b) Draw and high level state diagram of the above engine. [6 points] 11 CS 151 Digital Logic Design, Fall Quarter 2009 (c) Implement the DATAPATH of the above system by allocating components. You
may one or more registers and only one the encryption / decryption combination logic
described above. You may also use any logic gate that may be necessary. Draw the
implemented DATAPATH. [10 points] l
l
i
1 =7“
l 3 x <
i ..
l. S t A ,1 Age if 12 t, we—«mm—mmw ta
. m, $» ' ‘ Lung),
’53 x»: CS 151 Digital Logic Design, Fall Quarter 2009 (d) Show the interface between the CONTROLLER and the DATAPATH. Also show
the inputs and outputs of the CONTROLLER and the DATAPATH. [5 points] 13 (e) Draw the FSM of the controller. For each state show the values of all the outputs of the controller. Show the conditions for transition from one state to another. CS 151 Digital Logic Design, Fall Quarter 2009
[10 points] ;
mm, 14 ...
View
Full Document
 Spring '10
 AmrNady

Click to edit the document details