V30inst - 16-BIT V SERIESTM 16/8 AND 16-BIT MICROPROCESSORS INSTRUCTION V20TM V30TM V20HLTM V30HLTM V40TM V50TM V40HLTM V50HLTM V33ATM V53ATM 1996

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Unformatted text preview: 16-BIT V SERIESTM 16-/8- AND 16-BIT MICROPROCESSORS INSTRUCTION V20TM, V30TM V20HLTM, V30HLTM V40TM, V50TM V40HLTM, V50HLTM V33ATM V53ATM 1996 Document No. U11301EJ5V0UM00 (5th edition) Date Published June 1997 N Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. V20, V30, V20HL, V30HL, V40, V50, V40HL, V50HL, V33A, V53A, and V series are trademarks of NEC Corporation. InterTool is a trademark of Intermetrics Microsystems Software, Inc. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M7 96.5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 MAJOR REVISIONS IN THIS EDITION Pages Throughout Contents The following products have been deleted: PD70208 (A) (V40) PD70216 (A) (V50) PD70270 (V41TM) PD70280 (V51TM) The mark shows major revised points. PREFACE Readers This manual is intended for engineers who wish to understand the functions of the following 16-bit V series microprocessors and design application systems using them. Parts Number Nick Name V20 V30 V20HL V30HL V40 V50 V40HL V50HL V33A V53A PD70108 PD70116 PD70108H PD70116H PD70208 PD70216 PD70208H PD70216H PD70136A PD70236A Purpose This manual is to introduce the instruction functions of the above 16-bit V series microprocessors. Organization Two volumes of the User's Manual of the above 16- bit V series microprocessors are available: Hardware Manual and Instruction Manual (this manual). Hardware Manual General Pin Function CPU Function Internal Block Function Bus Control Function Interrupt Function Standby Function Reset Function Others Instruction Manual General Instruction Description Instruction Map Correspondence of Mnemonic between PD8086 and 8088 How to Read This Manual It is assumed that readers of this manual have a basic knowledge of electricity, logic circuits, and microcontrollers. Unless otherwise specified, the descriptions in this manual apply to all the models in the 16-bit V series microprocessors. Note that part number "PD70..." is referred to as "V..." in this manual. To check the details of the function of an instruction whose mnemonic is known, Refer to CHAPTER 2 INSTRUCTIONS (instructions are shown in alphabetic order of the mnemonic) To understand the details of each instruction, Read this manual in the order of the Table of Contents. To understand the hardware functions of each product, Refer to the User's Manual - Hardware (separate volume) for each product. To find the electrical specifications Refer to the data sheet for each product. Legend Data significance Active low Memory map address : Left: high, right: low : (top bar over pin or signal name) : Top: high, bottom: low in the following case: x: yH Note Caution Remark Numeric notation : Explanation of items marked with Note in the text : Important information : Supplement : Binary Decimal ... or B ... Address representation : x indicates a segment value, and y indicates an offset value Hexadecimal ... H Related documents The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. Document Parts Number V20 V30 V20HL V30HL V40 V50 V40HL Data Sheet User's Manual Hardware Instruction This manual IEU-761 Application Note Register Table Q&A IC-1827 IC-1828 IC-3552 IEM-871 U10154E U10666E U10911E Software U10554E IC-3659 U11610E U10037E Hardware Design U11123E V50HL U10911E Software V33A V53A U10136E U10120E U10032E U10108E U10188E Address Expansion, Software U10875E [MEMO] TABLE OF CONTENTS CHAPTER 1 1.1 1.2 1.3 GENERAL ............................................................................................................................ 1 Classification of Instructions by Function ........................................................................ 2 Instruction Word Format ..................................................................................................... 3 Functional Outline of Each Instruction .............................................................................. 3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.9 Data transfer instructions ........................................................................................................... 3 Block manipulation instructions .................................................................................................. 3 Bit field manipulation instructions ............................................................................................... 3 I/O instructions ........................................................................................................................... 4 Operation instructions ................................................................................................................ 4 BCD operation instructions ........................................................................................................ 4 BCD adjustment instructions ...................................................................................................... 5 Data conversion instruction ........................................................................................................ 5 Bit manipulation instructions ...................................................................................................... 5 1.3.10 Shift and rotate instructions ........................................................................................................ 5 1.3.11 Stack manipulation instructions .................................................................................................. 5 1.3.12 Program branch instructions ...................................................................................................... 6 1.3.13 CPU control instructions ............................................................................................................. 6 1.3.14 Mode select instructions ............................................................................................................. 6 CHAPTER 2 INSTRUCTIONS ................................................................................................................... 7 2.1 Description of Instructions (in alphabetical order of mnemonic) .................................... 7 2.2 Number of Instruction Execution Clocks ....................................................................... 169 APPENDIX A REGISTER CONFIGURATION ....................................................................................... 185 A.1 General-Purpose Registers (AW, BW, CW, DW) ............................................................ 185 A.2 Segment Registers (PS, SS, DS0, DS1) .......................................................................... 185 A.3 Pointers (SP, BP) ............................................................................................................. 185 A.4 Program Counter (PC) ..................................................................................................... 185 A.5 Program Status Word (PSW)........................................................................................... 186 A.6 Index Registers (IX, IY) .................................................................................................... 190 APPENDIX B ADDRESSING MODES .................................................................................................. 191 B.1 Instruction Address ......................................................................................................... 191 B.2 Memory Operand Address .............................................................................................. 193 APPENDIX C INSTRUCTION MAP ....................................................................................................... 199 APPENDIX D CORRESPONDENCE OF MNEMONICS OF PD8086 AND 8088 ................................ 203 APPENDIX E INSTRUCTION INDEX (mnemonic: by function) .......................................................... 205 APPENDIX F INSTRUCTION INDEX (mnemonic: alphabetical order) .............................................. 207 i LIST OF FIGURES Figure No. 1-1 1-2 1-3 2-1 A-1 Title Page Relations between Common Instructions and Dedicated Instructions of Each Model ........................... 1 Instruction Format .................................................................................................................................. 3 Operation of ALU When Operation Instruction Is Executed ................................................................... 4 Description Example ............................................................................................................................ 12 PSW Configuration ............................................................................................................................. 186 LIST OF TABLES Table No. 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 C-1 C-2 C-3 C-4 D-1 D-2 Title Page Classification of Instructions by Function ............................................................................................... 2 Example of Flag Operation .................................................................................................................... 7 Example of Operand Type ..................................................................................................................... 8 Example of Instruction Word .................................................................................................................. 9 Legend of Description of Instruction Format and Operand .................................................................. 10 Memory Addressing ............................................................................................................................. 11 Selecting 8-/16-Bit General-Purpose Register ..................................................................................... 11 Selecting Segment Register ................................................................................................................. 11 Number of Instruction Execution Clocks ............................................................................................ 170 Instruction Map ................................................................................................................................... 200 Group1, Group2, Imm, and Shift Codes ............................................................................................ 202 Group0 Codes .................................................................................................................................... 202 Group3 Codes .................................................................................................................................... 202 Register Correspondence with PD8086 and 8088 ........................................................................... 203 Mnemonic Correspondence with PD8086 and 8088 ....................................................................... 204 ii CHAPTER 1 GENERAL The 16-bit V series microprocessors have 101 common instructions that are completely compatible in terms of software, so that your software resources can be effectively utilized. In addition to these common instructions, the V20, V30, V20HL, V30HL, V40, V50, V40HL, and V50HL have three dedicated instructions (BRKEM, RETEM, and CALLN) to support emulation mode. The V33A and V53A have two dedicated instructions (BRKXA and RETXA) to support the extended address mode. Figure 1-1. Relations between Common Instructions and Dedicated Instructions of Each Model V20, V30, V20HL, V30HL, V40 V50 V40HL, V50HL, V33A, V53A Dedicated emulation mode instructions BRKEM RETEM CALLN 16-bit V series common instructions (101 types) Dedicated extended address mode instructions BRKXA RETXA Remark For the emulation mode and extended address mode, refer to the Hardware Manual of each model. 1 CHAPTER 1 GENERAL 1.1 Classification of Instructions by Function The instructions of the 16-bit V series can be broadly divided by classification of function into the following 27 types. Table 1-1. Classification of Instructions by Function Instruction Group Data transfer instructions Repeat prefix Primitive block transfer instructions Bit field manipulation instructions I/O instructions Primitive I/O instructions Add/subtract instructions BCD operation instructions Increment/decrement instructions Multiplication/division instructions BCD adjustment instructions Data conversion instructions Compare instructions Complement operation instructions Logical operation instructions Bit manipulation instructions Shift instructions Rotate instructions Subroutine control instructions Stack manipulation instructions Branch instruction Conditional branch instructions Interrupt instructions CPU control instructions Segment override prefix Dedicated emulation mode instructionsNote 1 Dedicated extended address mode instructionsNote 2 Mnemonic (alphabetical order) LDEA, MOV, TRANS, TRANSB, XCH REP, REPC, REPE, REPNC, REPNE, REPNZ, REPZ CMPBK, CMPBKB, CMPBKW, CMPM, CMPMB, CMPMW, LDM, LDMB, LDMW, MOVBK, MOVBKB, MOVBKW, STM, STMB, STMW EXT, INS IN, OUT INM, OUTM ADD, ADDC, SUB, SUBC ADD4S, CMP4S, ROL4, ROR4, SUB4S DEC, INC DIV, DIVU, MUL, MULU ADJ4A, ADJ4S, ADJBA, ADJBS CVTBD, CVTBW, CVTDB, CVTWL CMP NEG, NOT AND, OR, TEST, XOR CLR1, NOT1, SET1, TEST1 SHL, SHR, SHRA ROL, ROLC, ROR, RORC CALL, RET DISPOSE, POP, PREPARE, PUSH BR BC, BCWZ, BE, BGE, BGT, BH, BL, BLE, BLT, BN, BNC, BNE, BNH, BNL, BNV, BNZ, BP, BPE, BPO, BZ, BV, DBNZ, DBNZE, DBNZNE BRK, BRKV, CHKIND, RETI BUSLOCK, DI, EI, FPO1, FPO2, HALT, NOP, POLL DS0:, DS1:, PS:, SS: BRKEM, CALLN, RETEM BRKXA, RETXA Notes 1. Except V33A and V53A 2. V33A and V53A only 2 CHAPTER 1 GENERAL 1.2 Instruction Word Format Basically, an instruction word (object code) is in the following format. Figure 1-2. Instruction Format OP CODE Operand Remark op code : 8-bit code indicating type of instruction Operand : Field indicating register and memory address to be manipulated by instructions. Indicated as a field of 0 to 5 bytes. 1.3 Functional Outline of Each Instruction 1.3.1 Data transfer instructions The data transfer instructions transfer data between two registers and between a register and memory, without data manipulation. These instructions can be classified into the following four types. To transfer general data (MOV) : Transfers a specified byte/word from the second operand to the first operand. Can also directly transfer a numeric value to a register or memory. To transfer effective address (LDEA) : Transfers the offset address (effective address) of the second operand to the first operand. To transfer conversion table (TRANS) : Transfers 1 byte of a conversion table. Exchanges general data (XCH) : Exchanges the contents of the first operand with those of the second operand. 1.3.2 Block manipulation instructions A block (successive data) of bytes or words can be transferred or compared by using a repeat prefix and a primitive block transfer instruction. The primitive block transfer instructions transfer, compare, and scan data, like the instructions that transfer data with the accumulator in block units. If a 1-byte repeat prefix is used, repetitive processing by hardware can be performed so that data can be manipulated successively. 1.3.3 Bit field manipulation instructions The bit field manipulation instructions can be used to transfer data of specified length between a specified bit field area and the AW register, with a contiguous memory area regarded as the bit field. These instructions update a word offset (IX or IY register) and bit offset (8-bit general-purpose register) and automatically specify successive bit field data after the instructions have been executed. These instructions are useful for computer graphics and high-level languages and can support, for example, packed array of Pascal and data structure of record type. 3 CHAPTER 1 GENERAL 1.3.4 I/O instructions The I/O instructions and primitive I/O instructions can read/write I/O devices. The I/O devices transfer data with the CPU via the data bus by using these instructions. 1.3.5 Operation instructions The following instructions can execute 8-/16-bit data operations. Add/subtract, increment/decrement, multiplication, division, compare, complement operation, logical operation The increment/decrement instructions can increment (+1) or decrement (1) the 8-/16-bit data of the generalpurpose registers or memory. Each operation instruction is not executed in a register or memory whose contents are to be manipulated, but actually executed in the ALU. The result of the operation is set (1) or reset (0) to the flags of the program status word (PSW). Figure 1-3. Operation of ALU When Operation Instruction Is Executed Operation instruction Operation ALU Register Memory Data Set result of operation Flag Set status of operation result 1.3.6 BCD operation instructions The BCD operation instructions can be used to represent decimal numbers by using hexadecimal numbers for calculation. These instructions can also be used to execute arithmetic operation or comparison of BCD strings in memory. Instructions that support rotating the BCD strings are also included. Because the operand and comparison instructions are used to manipulate specific registers, they do not have an operand that specifies a packed BCD string. The first address of the source string (address of the byte data including LSD) is specified by the contents of the IX register in data segment 0 (DS0). The first address (address of the byte data including LSD) of the destination string is specified by the contents of the IY register in data segment 1 (DS1). The number of digits is specified by the contents of the CL register. Because the destination string and source string must be of the same length, 0 is extended to the length of longer string if the lengths of the two are different. 4 CHAPTER 1 GENERAL 1.3.7 BCD adjustment instructions BCD operation is supported by executing a BCD adjustment instruction before or after arithmetic operation. Because the BCD adjustment instructions are executed on the AL register, they do not have an operand. In the case of addition and subtraction, adjustment can be made to both packed BCD and unpacked BCD. In the case of multiplication and division, however, adjustment can be made to only unpacked BCD representation. 1.3.8 Data conversion instruction The data conversion instructions can convert the type and word length of binary and decimal numbers. The CVTBD and CVTDB instructions convert binary numbers and 2-digit unpacked BCD. The CVTBW and CVTWL instructions extend the sign in a register. 1.3.9 Bit manipulation instructions The bit manipulation instructions are used to execute logical operations on the bit data of the general-purpose registers or memory. The operand of the instruction format is "reg, bit" or "mem, bit". The first operand, reg or mem, specifies 8-/16-bit data including the bit data to be manipulated and codes a generalpurpose register or an effective address. The second operand bit indicates the address of the bit data in a byte or word, and uses the contents of CL or 8-bit immediate data. If reg or mem is 8-bit data, only the low-order 3 bits are the valid bit address. If reg or mem is 16-bit data, only the low-order 4 bits are the valid bit address, and the high-order bits are ignored. 1.3.10 Shift and rotate instructions The shift or rotate instructions shift or rotate the 8-/16-bit data of a general-purpose register or memory 1 bit or more (0 to 255). The shift instructions are divided into arithmetic shift and logical shift instructions. Usually, the number of digits to be shifted is 1, but it can be changed depending on the value of the CL register each time the instruction has been executed if specified by the count operand of the instruction (255 max.). The arithmetic shift instruction inserts 0 to the LSB of the data shifted if the data has been shifted 1 bit to the left, and 1 to the MSB of the data if the data has been shifted 1 bit to the right. The logical shift instruction does not cause the value of the LSB or MSB to be changed even when the data has been shifted 1 bit. Like the shift instructions, the number of digits to be rotated by a rotate instruction is specified by the count operand of the instruction. This value is the value stored to the CL register. As a result of executing the rotate instruction, the CY and V flags are affected. The bit rotated out is always stored to the CY flag. The V flag always becomes undefined if two or more digits have been rotated. If only one digit is rotated and the MSB (extension) of the destination is affected as a result, the V flag is set to 1; otherwise, the flag is reset to 0. The CY flag can be used as the extension of the destination when the ROLC or ROR instruction is used. 1.3.11 Stack manipulation instructions The stack manipulation instructions are used to manipulate the stack in the memory. The following four types of stack manipulation instructions are available. PUSH POP : Saves data to the stack. : Restores data from the stack. reference a global variable. DISPOSE : Restores the stack pointer (SP) and base pointer (BP) to the status before the PREPARE instruction is executed. PREPARE : Creates a stack frame and copies a frame pointer to secure an area for a local variable or to 5 CHAPTER 1 GENERAL 1.3.12 Program branch instructions These instructions branch program execution to specified addresses. The following four types of branch instructions are available. Subroutine control instructions : Save the contents of the program counter (PC) to the stack (CALL) or restore the contents of the PC from the stack (RET). Branch instruction : Branches the flow of an instruction to a specified address. on the value of a flag. Interrupt instructions : Temporarily stop execution of the program and controls flow of program execution by means of software interrupts if an external device requests for interrupt or if an operation error occurs. 1.3.13 CPU control instructions The CPU control instructions manipulate flags, synchronize the processor with an external device, or transfer data. An instruction that causes the CPU to execute nothing (NOP) is also available. 1.3.14 Mode select instructions (1) Emulation mode (except V33A and V53A) The mode can be changed between the native and emulation modes by using a dedicated emulation mode instruction. (2) Extended address mode (V33A and V53A only) The mode can be changed between the normal address mode and extended address mode by using a dedicated extended address mode instruction. Conditional branch instructions : Branch the flow of instruction execution to a specified address depending 6 CHAPTER 2 INSTRUCTIONS 2.1 Description of Instructions (in alphabetical order of mnemonic) This chapter explains the following items for each instruction. [Format] [Operation] [Operand] [Flag] [Description] [Example] [Number of bytes] [Word format] In [Format], [Operation], and [Operand], several identifiers are used. Tables 2-2 through 2-4 show the identifiers used and their meanings, and Tables 2-5 through 2-7 explain how to select memory addressing modes, general-purpose registers, and segment registers. [Flag] shows, by using identifiers, the operations of the flags that are affected as a result of executing the given instruction. Table 2-1 shows examples of operations of each flag. Table 2-1. Example of Flag Operation Identifier Blank 0 1 U R Description Not affected Reset to 0 Set to 1 Set to 1 or reset to 0 depending on result Undefined Restores previously saved value 7 CHAPTER 2 INSTRUCTIONS Table 2-2. Example of Operand Type Identifier reg 8-/16-bit general-purpose register (destination register for instruction using two 8-/16-bit general-purpose registers) reg' reg8 Source register for instruction using two 8-/16-bit general-purpose registers 8-bit general-purpose register (destination register for instruction using two 8-bit general-purpose registers) reg8' reg16 Source register for instruction using two 8-bit general-purpose registers 16-bit general-purpose register (destination register for instruction using two 16-bit general-purpose registers) reg16' mem mem8 mem16 mem32 dmem imm imm3 imm4 imm8 imm16 acc sreg src-table src-block dst-block near-proc far-proc near-label short-label far-label regptr16 memptr16 memptr32 pop-value fp-op R DS1-spec Seg-spec [ ] Source register for instruction using two 16-bit general-purpose registers 8-/16-bit memory address 8-bit memory address 16-bit memory address 32-bit memory address 16-bit direct memory address 8-/16-bit immediate data 3-bit immediate data 4-bit immediate data 8-bit immediate data 16-bit immediate data Accumulator (AW or AL) Segment register Name of 256-byte conversion table Name of source block addressed by IX register Name of destination block addressed by IY register Procedure in current program segment Procedure in other program segments Label in current program segment Label in range of end of instruction 128 to +127 bytes Label in other program segments 16-bit general-purpose register having offset of call address in current program segment 16-bit memory address having offset of call address in current program segment 32-bit memory address having offset and segment data of call address in other program segments Number of bytes discarded from stack (0 to 64K, usually even number) Immediate value identifying instruction code of floating-point coprocessor Register set (AW, BW, CW, DW, SP, BP, IX, IY) DS1 or segment name/group name ASSUMEd to DS1 Any segment register name or segment name/group name ASSUMEd to segment register Can be omitted Description 8 CHAPTER 2 INSTRUCTIONS Table 2-3. Example of Instruction Word Identifier W reg reg' mod, mem (disp-low) (disp-high) disp-low disp-high imm3 imm4 imm8 imm16-low imm16-high addr-low addr-high sreg s offset-low offset-high seg-low seg-high pop-value-low pop-value-high disp8 X XXX YYY ZZZ Operation codes of floating-point coprocessor Byte/word field (0, 1) Register field (000 to 111) Register field (000 to 111) (source register for instruction using two registers) Memory addressing specification bit (mod: 00 to 10, mem: 000 to 111) Low-order byte of option 16-bit displacement High-order byte of option 16-bit displacement Low-order byte of 16-bit displacement for PC relative addition High-order byte of 16-bit displacement for PC relative addition 3-bit immediate data 4-bit immediate data 8-bit immediate data Low-order byte of 16-bit immediate data High-order byte of 16-bit immediate data Low-order byte of 16-bit direct address High-order byte of 16-bit direct address Segment register specification bit (00 to 11) Sign extension specification bit (1: sign extension, 0: not sign extension) Low-order byte of 16-bit offset data loaded to PC High-order byte of 16-bit offset data loaded to PC Low-order byte of 16-bit segment data loaded to PS High-order byte of 16-bit segment data loaded to PS Low-order byte of 16-bit data specifying number of bytes discarded from stack High-order byte of 16-bit data specifying number of bytes discarded from stack 8-bit displacement relatively added to PC Description 9 CHAPTER 2 INSTRUCTIONS Table 2-4. Legend of Description of Instruction Format and Operand (1/2) Identifier dst dst1 dst2 src src1 src2 target AW AH AL BW CW CL DW BP SP PC PSW IX IY PS SS DS0 DS1 AC CY P S Z DIR IE V BRK MD (...) disp temp temp1 temp2 TA TB TC ext-disp8 seg offset Destination operand Destination operand Destination operand Source operand Source operand Source operand Target operand Accumulator (16 bits) Accumulator (high-order bytes) Accumulator (low-order bytes) BW register (16 bits) CW register (16 bits) CW register (low-order byte) DW register (16 bits) Base pointer (16 bits) Stack pointer (16 bits) Program counter (16 bits) Program status word (16 bits) Index register (source) (16 bits) Index register (destination) (16 bits) Program segment register (16 bits) Stack segment register (16 bits) Data segment 0 register (16 bits) Data segment 1 register (16 bits) Auxiliary carry flag Carry flag Parity flag Sign flag Zero flag Direction flag Interrupt enable flag Overflow flag Break mode Mode flag (not provided to V33A and V53A) Memory contents indicated by ( ) Displacement (8/16 bits) Temporary register (8/16/32 bits) Temporary register (16 bits) Temporary register (16 bits) Temporary register A (16 bits) Temporary register B (16 bits) Temporary register C (16 bits) 16-bits as result of sign-extending 8-bit displacement Immediate segment data (16 bits) Immediate offset data (16 bits) Description 10 CHAPTER 2 INSTRUCTIONS Table 2-4. Legend of Description on Instruction Format and Operand (2/2) Identifier + % Transfer direction Add Subtract Multiply Divide Modulo Logical product (AND) Logical sum (OR) Exclusive logical sum (XOR) 2-digit hexadecimal value 4-digit hexadecimal value Description ^ v v H H Table 2-5. Memory Addressing mem 000 001 010 011 100 101 110 111 mod BW+IX BW+IY BP+IX BP+IY IX IY Direct address BW 00 01 BW+IX+disp8 BW+IY+disp8 BP+IX+disp8 BP+IY+disp8 IX+disp8 IY+disp8 BP+disp8 BW+disp8 10 BW+IX+disp16 BW+IY+disp16 BP+IX+disp16 BP+IY+disp16 IX+disp16 IY+disp16 BP+disp16 BW+disp16 Table 2-6. Selecting 8-/16-Bit GeneralPurpose Register reg, reg' 000 001 010 011 100 101 110 111 W=0 AL CL DL BL AH CH DH BH W=1 AW CW DW BW SP BP IX IY Table 2-7. Selecting Segment Register sreg 00 01 10 11 DS1 PS SS DS0 11 CHAPTER 2 INSTRUCTIONS Figure 2-1. Description Example Mnemonic Function ADD Describes basic description format of instruction by using symbols. Describes operation of instruction by using symbols. Describes operands that can be specified for this instruction. For the description of the symbol of each operand, refer to Tables 2-2 through 2-4. Addition Add ADD dst, src dstdst+src Mnemonic ADD Operand (dst, src) reg, reg' mem, reg [Format] [Operation] [Operand] Full name Describes operation of flags that are affected as a result of instruction execution. For the symbol of each flag, refer to Table 2-4. For the symbol of flag operation, refer to Table 2-1. Describes the operation of the instruction in detail. [Flag] AC CY V P S Z [Description] Adds the contents of the destination operand (dst) specified by the first operand ... Shows an example of description based on the description format of RA70116-I (InterToolTM). [Example] MOV AW, 0 . . . Indicates the instruction word length. [Number of bytes] Mnemonic ADD Operand reg, reg' mem, reg No. of Bytes 2 2-4 Indicates the instruction format. For the symbol of each field, refer to Table 2-3. The Operation Code column shows the following byte order (6 bytes max.). Operation Code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 First byte Third byte Fifth byte Second byte Fourth byte Sixth byte [Word format] Mnemonic Operand Operation Code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ADD reg, reg' mem, reg' 0 0 0 0 0 0 0 W 1 1 0 0 0 0 0 0 0 W mod reg reg reg' mem 12 CHAPTER 2 INSTRUCTIONS ADD [Format] [Operand, Operation] ADD dst, src Addition Add Mnemonic ADD Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm dst dst + src Operation [When W = 0] AL AL + imm8 [When W = 1] AW AW + imm16 [Flag] AC CY V P S Z [Description] Adds the contents of the destination operand (dst) specified by the first operand to the contents of the source operand (src) specified by the second operand, and stores the result to the destination operand (dst). [Example] To add the contents of memory 0:50H (word data) to the contents of the DW register, and store the result to 0:50H MOV MOV MOV ADD AW, 0 DS1, AW IY, 50H DS1: WORD PTR [IY], DW [Number of bytes] Mnemonic ADD reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm Operand No. of bytes 2 2-4 2-4 3, 4 3-6 2, 3 13 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic ADD reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 W 1 1 0 0 0 0 0 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 0 0 0 0 1 W mod (disp-low) reg, imm 1 0 0 0 0 0 s W 1 1 0 0 0 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 s W mod 0 0 0 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 0 0 0 1 0 W imm16-high 14 CHAPTER 2 INSTRUCTIONS ADD4S [Format] ADD4S [DS1-spec:] dst-string, [Seg-spec:] src-string ADD4S [Operation] [Operand] BCD string (IY, CL) BCD string (IY, CL) + BCD string (IX, CL) Decimal addition Add Nibble String Mnemonic ADD4S Operand (dst, src) [DS1-spec : ] dst-string, [Seg-spec : ] src-string None [Flag] AC CY U V U P U S U Z [Description] Adds the packed BCD string addressed by the IX register to the packed BCD string addressed by the IY register, and stores the the result of the string addressed by the IY register. The string length (number of BCD digits) is determined by the CL register (the number of digits is d if the contents of CL is d) in a range of 1 to 254 digits. The destination string must be always located in a segment specified by the DS1 register, the segment cannot be overridden. Although the default segment register of the source string is the DS0 register, the segment can be overridden, and the string can be located in a segment specified by any segment register. The format of a packed BCD string is as follows. Byte offset +m Memory +CL Digit offset +4 +3 +2 +1 0 +1 +0 IX IY Caution The BCD string instruction always operates in units of an even number of digits. If an even number of digits is specified, therefore, the result of the operation and each flag operation are normal. If an odd number of digits is specified, however, an operation of an even number of digits, or an odd number of digits + 1, is executed. As a result, the result of the operation is an even number of digits and each flag indicates an even number of digits. To specify an odd number of digits, therefore, keep this in mind: Execute the BCD addition instruction, if the number of digits is odd, after clearing the high-order 4 bits of the most significant byte to "0". As a result, the carry is indicated by bit 4 of the most significant byte, and is not reflected in the flag. 15 CHAPTER 2 INSTRUCTIONS [Example] MOV MOV MOV ADD4S IX, OFFSET IY, OFFSET CL, 4 VAR_1 VAR_2 [Number of bytes] [Word format] 2 Mnemonic ADD4S Operand [DS1-spec :] dst-string, [Seg-spec :] src-string None Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 16 CHAPTER 2 INSTRUCTIONS ADDC [Format] [Operand, Operation] Mnemonic ADDC Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm Addition with carry Add with Carry ADDC dst, src Operation dst dst + src + CY [When W = 0] AL AL + imm8 + CY [When W = 1] AW AW + imm16 + CY [Flag] AC CY V P S Z [Description] Adds the contents of the destination operand (dst) specified by the first operand to the contents of the source operand (src) specified by the second operand with the contents of the CY flag, and stores the result to the destination operand (dst). [Example] SET1 XOR MOV ADDC CY AW, AW AW, BW ; Sets CY flag to 1. ; AW = 0 ; Contents of AW register = 100H BW, 0FFH ; BW = 0FFH [Number of bytes] Mnemonic ADDC reg, reg' mem, reg reg, mem reg, imm Operand No. of bytes 2 2-4 2-4 3, 4 3-6 2, 3 mem, imm acc, imm 17 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic ADDC reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 W 1 1 0 0 0 1 0 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 0 1 0 0 1 W mod (disp-low) reg, imm 1 0 0 0 0 0 s W 1 1 0 1 0 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 s W mod 0 1 0 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 0 1 0 1 0 W imm16-high 18 CHAPTER 2 INSTRUCTIONS ADJ4A [Format] [Operation] ADJ4A Where AL ^ 0FH > 9 or AC = 1, AL AL + 6 AC 1 Where AL > 9FH or CY = 1 AL AL + 60H CY 1 [Operand] Mnemonic ADJ4A None Packed decimal adjustment of result of addition Adjust Nibble Add Operand [Flag] AC CY V U P S Z [Description] Adjusts the contents of the AL register resulting from addition of two packed decimal numbers into one packed decimal number. [Example] [Number of bytes] [Word format] ADJ4A 1 Mnemonic ADJ4A None Operand Operation code 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 19 CHAPTER 2 INSTRUCTIONS ADJ4S [Format] [Operation] ADJ4S Packed decimal adjustment of result of subtraction Adjust Nibble Subtract Where AL ^ 0FH > 9 or AC = 1 AL AL 6 AC 1 Where AL > 9FH or CY = 1 AL AL 60H CY 1 [Operand] Mnemonic ADJ4S None Operand [Flag] AC CY V U P S Z [Description] Adjusts the contents of the AL register resulting from subtracting two packed decimal numbers into one packed decimal number. [Example] SUB ADJ4S AW, BW [Number of bytes] [Word format] 1 Mnemonic ADJ4S None Operand Operation code 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 1 20 CHAPTER 2 INSTRUCTIONS ADJBA [Format] [Operation] ADJBA Unpacked decimal adjustment of result of addition Adjust Byte Add Where AL ^ 0FH > 9 or AC = 1 AL AL + 6 AH AH + 1 AC 1 CY AC AL AL ^ 0FH [Operand] Mnemonic ADJBA None Operand [Flag] AC CY V U P U S U Z U [Description] Adjusts the contents of the AL register resulting from adding two unpacked decimal numbers into one unpacked decimal number. The high-order 4 bits become 0. [Example] [Number of bytes] [Word format] ADJBA 1 Mnemonic ADJBA None Operand Operation code 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 21 CHAPTER 2 INSTRUCTIONS ADJBS [Format] [Operation] ADJBS Unpacked decimal adjustment of result of subtraction Adjust Byte Subtract Where AL ^ 0FH > 9 or AC = 1 AL AL 6 AH AH 1 AC 1 CY AC AL AL ^ 0FH [Operand] Mnemonic ADJBS None Operand [Flag] AC CY V U P U S U Z U [Description] Adjusts the contents of the AL register resulting from subtracting two unpacked decimal numbers into one unpacked decimal number. The high-order 4-bits become 0. [Example] SUB ADJBS AW, BW [Number of bytes] [Word format] 1 Mnemonic ADJBS None Operand Operation code 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 22 CHAPTER 2 INSTRUCTIONS AND [Format] [Operand, Operation] Mnemonic AND Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm dst dst ^ src Logical product And AND dst, src Operation [When W = 0] AL AL ^ imm8 [When W = 1] AW AW ^ imm16 [Flag] AC CY U 0 V 0 P S Z [Description] ANDs the contents of the destination operand (dst) specified by the first operand to the contents of the source operand (src) specified by the second operand, and stores the result to the destination operand (dst). [Example] MOV AND DW, IY DW, 7FFFH [Number of bytes] Mnemonic AND reg, reg' mem, reg reg, mem reg, imm Operand No. of bytes 2 2-4 2-4 3, 4 3-6 2, 3 mem, imm acc, imm 23 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic AND reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 W 1 1 0 0 1 0 0 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 1 0 0 0 1 W mod (disp-low) reg, immNote 1 0 0 0 0 0 0 W 1 1 1 0 0 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 0 W mod 1 0 0 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 1 0 0 1 0 W imm16-high Note The following code may be created depending on the assembler or compiler used. 7 6 5 4 3 2 1 0 7 6 5 4 3 1 0 0 0 0 0 1 W 1 1 1 0 0 imm8 2 1 0 reg Even in this case, the instruction is executed normally. Note, however, that some emulators do not support the functions to disassemble and assemble this instruction. 24 CHAPTER 2 INSTRUCTIONS BC BL [Format] BC BL [Operation] [Operand] short-label short-label Conditional branch where CY = 1 Branch if Carry Branch if Lower Where CY = 1: PC PC + ext-disp8 Mnemonic BC BL Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC when the CY flag is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] TEST BC . . . TEST BL . . . LP4: AL, BL SHORT AL, BL SHORT LP5 ; LP5 = label LP4 ; LP4 = label [Number of bytes] [Word format] 2 Mnemonic BC BL Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 0 0 1 0 disp8 25 CHAPTER 2 INSTRUCTIONS BCWZ [Format] [Operation] [Operand] BCWZ short-label Where CW = 0: PC PC + ext-disp8 Conditional branch where CW = 0 Branch if CW equals Zero Mnemonic BCWZ Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the value of the CW register is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. If the above condition is not satisfied, execution goes on to the next instruction. [Example] LP22: . . . ADD BCWZ AL, BL LP22 ; LP22 = label SHORT [Number of bytes] [Word format] 2 Mnemonic BCWZ Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 0 0 1 1 disp8 26 CHAPTER 2 INSTRUCTIONS BE BZ [Format] BE BZ [Operation] [Operand] short-label short-label Conditional branch where Z = 1 Branch if Equal Branch if Zero Where Z = 1: PC PC + ext-disp8 Mnemonic BE BZ Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the Z flag is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] AND BE . . . OR BZ . . . LOOP: AL, 2 SHORT AH, BH SHORT LOOP1 ; LOOP1 = label LOOP ; LOOP = label [Number of bytes] [Word format] 2 Mnemonic BE BZ Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 0 1 0 0 disp8 27 CHAPTER 2 INSTRUCTIONS BGE [Format] [Operation] [Operand] BGE short-label Where S v V = 0: PC PC + ext-disp8 Conditional branch where S v V = 0 Branch if Greater Than or Equal Mnemonic BGE Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the result of exclusive OR (XOR) between the S and V flags is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. Execution goes on to the next instruction if the above condition is not satisfied. [Example] SHL BGE . . . LP16: AL, 1 SHORT LP16 ; LP16 = label [Number of bytes] [Word format] 2 Mnemonic BGE Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 1 0 1 disp8 28 CHAPTER 2 INSTRUCTIONS BGT [Format] [Operation] [Operand] BGT short-label (S v V) v Z = 0: PC PC + ext-disp8 Conditional branch where (S v V) v Z = 0 Branch if Greater Than Mnemonic BGT Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the result of ORing between the result of exclusive OR (XOR) of the S and V flags, and the Z flag is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. Execution goes on to the next instruction if the above condition is not satisfied. [Example] LP18: . . . SHL BGT AL, 1 LP18 [Number of bytes] [Word format] 2 Mnemonic BGT Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 disp8 29 CHAPTER 2 INSTRUCTIONS BH [Format] [Operation] [Operand] BH short-label Where CY v Z = 0: PC PC + ext-disp8 Conditional branch where CY v Z = 0 Branch if Higher Mnemonic BH Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the result of ORing the CY and Z flags is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] ROL BH . . . LP10: AL, 1 SHORT LP10 ; LP10 = label [Number of bytes] [Word format] 2 Mnemonic BH Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 1 disp8 30 CHAPTER 2 INSTRUCTIONS BLE [Format] [Operation] [Operand] BLE short-label (S v V) v Z = 1: PC PC + ext-disp8 Conditional branch where (S v V) v Z = 1 Branch if Less than or Equal Mnemonic BLE Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the result of ORing between the result of exclusive OR (XOR) of the S and V flags, and the Z flag is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. Execution goes on to the next instruction if the above condition is not satisfied. [Example] LP17: . . . SHR BLE AL, 1 SHORT LP17 [Number of bytes] [Word format] 2 Mnemonic BLE Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 0 disp8 31 CHAPTER 2 INSTRUCTIONS BLT [Format] [Operation] [Operand] BLT short-label Where S v V = 1: PC PC + ext-disp8 Conditional branch where S v V = 1 Branch if Less Than Mnemonic BLT Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the result of exclusive OR between the S and Z flags is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. Execution goes on to the next instruction if the above condition is not satisfied. [Example] ADD BLT . . . LP15: AL, BL SHORT LP15 ; LP15 = label [Number of bytes] [Word format] 2 Mnemonic BLT Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 1 0 0 disp8 32 CHAPTER 2 INSTRUCTIONS BN [Format] [Operation] [Operand] BN short-label Where S = 1: PC PC + ext-disp8 Conditional branch where S = 1 Branch if Negative Mnemonic BN Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the S flag is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] ADD AL, BL BN LP11 ; LP11 = label . . . LP11: [Number of bytes] [Word format] 2 Mnemonic BN Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 0 disp8 33 CHAPTER 2 INSTRUCTIONS BNC BNL [Format] BNC short-label BNL short-label [Operation] [Operand] Where CY = 0: PC PC + ext-disp8 Conditional branch where CY = 0 Branch if Not Carry Branch if Not Lower Mnemonic BNC BNL Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the CY flag is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] ROR BNC . . . ROR BNL . . . LP6: AL, 1 SHORT LP6 AL, 1 SHORT LP7 ; LP7 = label ; LP6 = label [Number of bytes] [Word format] 2 Mnemonic BNC BNL Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 0 0 1 1 disp8 34 CHAPTER 2 INSTRUCTIONS BNE BNZ [Format] BNE short-label BNZ short-label [Operation] [Operand] Where Z = 0: PC PC + ext-disp8 Conditional branch where Z = 0 Branch if Not Equal Branch if Not Zero Mnemonic BNE BNZ Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the Z flag is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] OR BNE . . . AND BNZ . . . LP8: AL, BL SHORT LP8 SH, BH SHORT LP9 ; LP9 = label ; LP8 = label [Number of bytes] [Word format] 2 Mnemonic BNE BNZ Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 0 1 0 1 disp8 35 CHAPTER 2 INSTRUCTIONS BNH [Format] [Operation] [Operand] BNH short-label Where CY v Z = 1: PC PC + ext-disp8 Conditional branch where CY v Z = 1 Branch if Not Higher Mnemonic BNH Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the result of OR between the CY and Z flags is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] ROR BNH . . . LP9: AL, 1 SHORT LP9 ; LP9 = label [Number of bytes] [Word format] 2 Mnemonic BNH Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 0 disp8 36 CHAPTER 2 INSTRUCTIONS BNV [Format] [Operation] [Operand] BNV short-label Where V = 0: PC PC + ext-disp8 Mnemonic BNV Operand short-label Conditional branch where V = 0 Branch if not Overflow [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the V flag is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] ROR AL, 1 BNV LP3 . . . LP3: [Number of bytes] [Word format] 2 Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 BNV short-label 0 1 1 1 0 0 0 1 disp8 Mnemonic Operand 37 CHAPTER 2 INSTRUCTIONS BP [Format] [Operation] [Operand] BP short-label Where S = 0: PC PC + ext-disp8 Conditional branch where S = 0 Branch if Positive Mnemonic BP Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the S flag is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] SHR AL, 1 BP SHORT LP12 ; LP12 = label . . . LP12: [Number of bytes] [Word format] 2 Mnemonic BP Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 1 disp8 38 CHAPTER 2 INSTRUCTIONS BPE [Format] [Operation] [Operand] BPE short-label Where P = 1: PC PC + ext-disp8 Mnemonic BPE Operand short-label Conditional branch where P = 1 Branch if Parity Even [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the P flag is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] ADD AL, BL BPE SHORT LP13 ; LP13 = label . . . LP13: [Number of bytes] [Word format] 2 Mnemonic BPE Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 0 1 0 disp8 39 CHAPTER 2 INSTRUCTIONS BPO [Format] [Operation] [Operand] BPO short-label Where P = 0: PC PC + ext-disp8 Conditional branch where P = 0 Branch if Parity Odd Mnemonic BPO Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC if the P flag is 0. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] ADD AL, BL BPO SHORT LP14 ; LP14 = label . . . LP14: [Number of bytes] [Word format] 2 Mnemonic BPO Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 1 0 1 1 disp8 40 CHAPTER 2 INSTRUCTIONS BR [Format] [Operation, operand] Mnemonic BR Operand (target) near-label short-label regptr16 memptr16 far-label memptr32 PS seg PC offset PC PC + disp Unconditional branch Branch BR target Operation PC PC + ext-disp8 PC target PS (memptr32 + 3, memptr32 + 2) PC (memptr32 + 1, memptr32) [Flag] AC CY V P S Z [Description] When target = near-label Transfers the current PC value with a 16-bit displacement (disp) added to the PC. If the branch address is within a segment where this instruction is placed, the assembler automatically executes this instruction. When target = short-label Transfers the current PC value with an 8-bit displacement added (actually, signextended 16 bits (ext-disp8)) to the PC. If the branch address is within a segment where this instruction is placed, and within a range of 127 bytes, the assembler automatically executes this instruction. When target = regptr16 or target = memptr16 Transfers the contents of the target operand (target) to the PC. Execution can branch to any address in the segment where this instruction is placed. When target = far-label Transfers the 16-bit offset data at the second and third byte positions of the instruction to the PC, and the 16-bit segment data at the fourth and fifth byte position of the instruction to the PS. Execution can branch to any address of any segment. When target = memptr32 Loads the high-order 2 bytes of a 32-bit memory area to the PS, and the low-order 2 bytes, to the PC. Execution can branch to any address of any segment. 41 CHAPTER 2 INSTRUCTIONS [Example] [Number of bytes] BR $ 8 Mnemonic BR near-label Operand No. of bytes 3 2 2 2-4 5 2-4 short-label regptr16 memptr16 far-label memptr32 [Word format] Mnemonic BR Operand near-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 1 0 0 1 disp-high disp-low -- disp8 reg mem short-label regptr16 memptr16 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 mod 1 0 0 (disp-low) (disp-high) offset-low seg-low -- far-label 1 1 1 0 1 0 1 0 offset-high seg-high memptr32 1 1 1 1 1 1 1 1 mod 1 0 1 (disp-low) (disp-high) mem 42 CHAPTER 2 INSTRUCTIONS BRK [Format] [Operand, operation] Mnemonic BRK 3 Operand (target) Software trap Break BRK target Operation TA (00DH, 00CH) TC (00FH, 00EH) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP + 1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA TA (imm8 4 + 1, imm8 4) TC (imm8 4 + 3, imm8 4 + 2) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP + 1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA imm8 ( 3) [Flag] AC CY V P S Z IE BRK 0 0 [Description] Saves the values of PSW, PS, and PC to the stack and resets the IE and BRK flags to 0. Then loads the low-order 2 bytes of vector 3 in the interrupt vector table to the PC, and the high-order 2 bytes to the PS if target = 3. If target = imm8, loads the low-order 2 bytes of the interrupt vector table (4 bits) specified by the 8-bit immediate data to the PC, and the high-order 2 bytes to the PS. [Example] BRK 3 BRK 5 [Number of bytes] Mnemonic BRK 3 imm8 Operand No. of bytes 1 2 [Word format] Mnemonic BRK 3 imm8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 -- imm8 43 CHAPTER 2 INSTRUCTIONS BRKEM [except V33A and V53A] [Format] [Operation] BRKEM imm8 TA (imm8 4 + 1, imm8 4) TC (imm8 4 + 3, imm8 4 + 2) SP SP 2, (SP + 1, SP) PSW MD 0: Write enable status SP SP 2, (SP + 1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA [Operand] Starts emulation mode Break for Emulation Mnemonic BRKEM imm8 Operand [Flag] AC CY V P S Z MD 0 [Description] This instruction starts the emulation mode. The values of the PSW, PS, and PC are saved to the stack, the MD flag is reset to 0 to enable writing, and execution jumps to the emulation address specified by the interrupt vector specified by the 8-bit immediate data described as an operand. When the instruction code of the interrupt service routine (for emulation) to which execution has jumped is fetched, the CPU interprets this code as an instruction of the PD8080AF and executes. To return to the native mode from the emulation mode, use the RETEM or CALLN instruction. [Example] [Number of bytes] [Word format] BRKEM 40H 3 Mnemonic BRKEM imm8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 imm8 -- 44 CHAPTER 2 INSTRUCTIONS BRKV [Format] [Operation] BRKV Where V = 1, TA (011H, 010H) TC (013H, 012H) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP + 1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA [Operand] Overflow exception Break if Overflow Mnemonic BRKV None Operand [Flag] AC CY V P S Z IE BRK 0 0 [Description] Saves the values of PSW, PS, and PC to the stack and resets the IE and BRK flags to 0 if the V flag is set to 1. Then loads the low-order 2 bytes of vector 4 of the interrupt vector table to the PC and the high-order 2 bytes to the PS if target = 3. Execution proceeds to the next instruction if the V flag is reset to 0. [Example] [Number of bytes] [Word format] BRKV 1 Mnemonic BRKV None Operand Operation code 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 45 CHAPTER 2 INSTRUCTIONS BRKXA [V33A and V53A only] [Format] [Operation] BRKXA imm8 temp1 (imm8 4 + 1, imm8 4) temp2 (imm8 4 + 3, imm8 4 + 2) XA 1 PC temp1 PS temp2 [Operand] Starts extended address mode Break Extended Address Mode Mnemonic BRKXA imm8 Operand [Flag] AC CY V P S Z [Description] Starts the extended address mode. Transfers control to an address stored to the entry of the interrupt vector table specified by the operand, and sets the XA flag of the XAM register (internal I/O address: FF80H) to 1. If this instruction is executed in the normal address mode, the vector table on the address in the normal address mode is read and then the extended address mode is set. Execution jumps to the address of the vector table read first. If this instruction is executed in the extended address mode, the vector table on the address in the extended address mode is read, and execution jumps to the address of this vector table. The values of PC, PS, and PSW are not saved to the stack. To return from the extended address mode, use the RETXA instruction. Note that execution cannot be returned from this mode by the RETI instruction. [Example] [Number of bytes] [Word format] BRKXA 0AH 3 Mnemonic BRKXA imm8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 imm8 -- 46 CHAPTER 2 INSTRUCTIONS BUSLOCK [Format] [Operation] [Operand] BUSLOCK Bus Lock Prefix Bus lock prefix Bus Lock Prefix Mnemonic BUSLOCK None Operand [Flag] AC CY V P S Z [Description] V20, V30, V20H, and V30HL In large-scale mode : Outputs the bus lock signal (BUSLOCK) while the single instruction following this instruction is executed. If this instruction is used for a block processing instruction with a repeat prefix, the BUSLOCK signal is continuously output until the block processing is completed. In small-scale mode : Although the BUSLOCK signal is not output, the bus hold request is disabled while the BUSLOCK signal is output in the large-scale mode. Therefore, this instruction is useful for not accepting the bus hold request during block processing. Cautions 1. Do not place this instruction immediately before the POLL instruction. 2. The hardware interrupt requests (NMI and INT) and single-step break are not accepted between this instruction and the next instruction. Other than V20, V30, V20HL, and V30HL Outputs the bus lock signal (BUSLOCK) while the single instruction following this instruction is executed. If this instruction is used for a block processing instruction with a repeat prefix, the BUSLOCK signal is continuously output until the block processing is completed. Cautions 1. Do not place this instruction immediately before the POLL instruction. 2. The hardware interrupt requests (maskable interrupt and non- maskable interrupt) and single-step break are not accepted between this instruction and the next instruction. [Example] [Number of bytes] [Word format] BUSLOCK REP MOVBKB 1 Operation code 7 6 5 4 3 2 1 0 BUSLOCK None 1 1 1 1 0 0 0 0 Mnemonic Operand 47 CHAPTER 2 INSTRUCTIONS BV [Format] [Operation] [Operand] BV short-label Where V= 1: PC PC + ext-disp8 Conditional branch where V = 1 Branch if Overflow Mnemonic BV Operand short-label [Flag] AC CY V P S Z [Description] Loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC when the V flag is 1. Execution can be branched in a segment where this instruction is placed and in an address range of 128 to +127 bytes. [Example] LP2: . . . SHL AL, 1 BV SHORT LP2 [Number of bytes] [Word format] 2 Mnemonic BV Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 1 0 0 0 0 disp8 48 CHAPTER 2 INSTRUCTIONS CALL [Format] [Operand, operation] Mnemonic CALL Operand (target) near-proc Subroutine call Call CALL target Operation SP SP 2 (SP + 1, SP) PC PC PC + disp SP SP 2 (SP + 1, SP) PC PC regptr16 TA (memptr16 + 1, memptr16) SP SP 2 (SP + 1, SP) PC PC TA SP SP 2 (SP + 1, SP) PS PS seg SP SP 2 (SP + 1, SP) PC PS offset TA (memptr32 + 1, memptr32) TB (memptr32 + 3, memptr32 + 2) SP SP 2 (SP + 1, SP) PS PS TB SP SP 2 (SP + 1, SP) PC PC TA regptr16 memptr16 far-proc memptr32 [Flag] AC CY V P S Z [Description] When target = near-proc or target = regptr16 Saves the value of the PC to the stack and then transfers the next contents of the target operand (target) to the PC. When target = near-proc : 16-bit relative address When target = regptr16 : Value of 16-bit register (offset) When target = memptr16 Saves the value of the PC to the stack and then transfers the contents of a 16-bit memory area (offset) addressed by the target operand (target) to the PC. Any address in the segment where this instruction is placed can be called. 49 CHAPTER 2 INSTRUCTIONS When target = far-proc Saves the values of PC and PS to the stack and transfers the second and third bytes of the instruction to the PC, and the fourth and fifth bytes to the PS. This instruction can call any address in any segment. When target = memptr32 Saves the values of PC and PS to the stack and transfers the high-order 2 bytes of a 32-bit memory area addressed by the target operand (target) to the PS and the loworder 2 bytes to the PC. This instruction can call any address in any segment. [Example] CALL $ + 10 CALL SUB1 ; SUB1 is label [Number of bytes] Mnemonic CALL near-proc regptr16 memptr16 far-proc memptr32 Operand No. of bytes 3 2 2-4 5 2-4 [Word format] Mnemonic CALL Operand near-proc Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 1 0 0 0 disp-high disp-low -- reg mem regptr16 memptr16 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 mod 0 1 0 (disp-low) (disp-high) offset-low seg-low -- far-proc 1 0 0 1 1 0 1 0 offset-high seg-high memptr32 1 1 1 1 1 1 1 1 mod 0 1 1 (disp-low) (disp-high) mem 50 CHAPTER 2 INSTRUCTIONS CALLN [except V33A and V53A] [Format] [Operation] CALLN imm8 TA (imm8 4 + 1, imm8 4) TC (imm8 4 + 3, imm8 4 + 2) SP SP 2, (SP + 1, SP) PSW MD 1 SP SP 2, (SP + 1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA [Operand] Native mode call Call Native Mnemonic CALLN imm8 Operand [Flag] AC CY V P S Z MD 1 [Description] When this instruction is executed in the emulation mode (this instruction is interpreted as an instruction of the PD8080AF), the CPU saves the values of PS, PC, and PSW to the stack (at this time, MD = 0 is saved), sets the MD flag to 1, and loads an interrupt vector specified by the 8-bit immediate data described as an operand to the PS and PC. In this way, an interrupt routine in the native mode can be called from the emulation mode. To return to the emulation mode from this interrupt routine, use the RETI instruction. [Example] [Number of bytes] [Word format] CALLN 40H 3 Mnemonic CALLN imm8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 imm8 -- 51 CHAPTER 2 INSTRUCTIONS CHKIND [Format] [Operation] CHKIND reg16, mem32 When (mem32) > reg16 or (mem32 + 2) < reg16 TA (015H, 014H) TC (017H, 016H) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP +1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA [Operand] Index value check Check Index Mnemonic CHKIND Operand reg16, mem32 [Flag] If interrupt condition is satisfied AC CY V P S Z IE BRK 0 0 If interrupt condition is not satisfied AC CY V P S Z IE BRK [Description] This instruction checks whether an index value that specifies an element is in a defined area if the data structure is of array type. If the index exceeds the defined area, the BRK 5 instruction is started. The defined area value is set to 2 words in memory in advance (the first word is the lower-limit value and the second word is the higher-limit value). As the index value, the register (any 16-bit register) used by an array manipulation program is used. Upper limit Lower limit ,, ,, Array element Memory 15 mem32 0 (Lower limit) mem32+2 (Upper limit) 52 CHAPTER 2 INSTRUCTIONS [Example] [Number of bytes] [Word format] CHKIND AW, DWORD_VAR 2 to 4 Mnemonic CHKIND Operand reg16, mem32 Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 0 0 0 1 0 mod (disp-low) reg (disp-high) mem 53 CHAPTER 2 INSTRUCTIONS CLR1 [Format] (1) CLR1 dst, src (2) CRL1 dst [Operation] Format (1): Bit n of dst (n is specified by src) 0 Format (2): dst 0 [Operand] Format (1) Mnemonic CLR1 Operand (dst, src) reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 Resets bit Clear bit Format (2) Mnemonic CLR1 CY DIR Operand (dst) [Flag] Format (1) AC CY V P S Z Format (2) (when dst = CY) AC CY 0 V P S Z Format (2) (when dst = DIR) AC CY V P S Z DIR 0 54 CHAPTER 2 INSTRUCTIONS [Description] Format (1) : Resets bit n (n is the contents of the source operand (src) specified by the second operand) of the destination operand (dst) specified by the first operand, and stores the result to the destination operand (dst). If the operand is reg8, CL or mem8, CL, only the low-order 3 bits (0 to 7) of the value of CL are valid. If the operand is reg16, CL or mem16, CL, only the low-order 4 bits (0 to 15) of the value of CL are valid. If the operand is reg8, imm3, only the low-order 3 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem8, imm3, only the low-order 3 bits of the immediate data at the last byte position of the instruction are valid. If the operand is reg16, imm4, only the low-order 4 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem16, imm4, only the low-order 4 bits of the immediate data at the last byte of the instruction are valid. Format (2) : Resets the CY flag if dst = CY. Resets the DIR flag if dst = DIR. Also sets so that the index registers (IX and IY) are auto-incremented when MOVBK, CMPBK, CMPM, LDM, STM, INM, or OUTM instruction is executed. [Example] CLR1 SHL BC CY AL,1 $+6 [Number of bytes] Mnemonic CLR1 reg8, CL mem8, CL reg16, CL Operand No. of bytes 3 3-5 3 3-5 4 4-6 4 4-6 1 1 mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 CY DIR 55 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic CLR1 reg8, CL Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 0 1 1 0 0 0 reg -- mem8, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 0 mod 0 0 0 (disp-high) mem (disp-low) -- reg16, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 reg -- mem16, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 mod 0 0 0 (disp-high) mem (disp-low) -- reg8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 1 1 0 0 0 reg imm3 mem8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 mod 0 0 0 (disp-high) mem (disp-low) imm3 reg16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 reg imm4 mem16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 mod 0 0 0 (disp-high) mem (disp-low) imm4 -- -- CY DIR 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 56 CHAPTER 2 INSTRUCTIONS CMP [Format] [Operand, operation] Mnemonic CMP Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm [When W = 0] AL imm8 [When W = 1] AW imm16 dst src Operation Compare Compare CMP dst, src [Flag] AC CY V P S Z [Description] Subtracts the source operand (src) specified by the second operand from the destination operand (dst) specified by the first operand. The result of the subtraction is stored nowhere, and only the flags are affected. [Example] CMP BL, BYTE PTR [IX] CMP CW, [BP+4] [Number of bytes] Mnemonic CMP reg, reg' mem, reg reg, mem reg, imm Operand No. of bytes 2 2-4 3, 4 3-6 2, 3 mem, imm acc, imm 57 CHAPTER 2 INSTRUCTIONS [Format] Mnemonic CMP reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 1 1 1 0 1 W 1 1 0 0 1 1 1 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 1 1 1 0 1 W mod (disp-low) reg, imm 1 0 0 0 0 0 s W 1 1 1 1 1 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 s W mod 1 1 1 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 1 1 1 1 0 W imm16-high 58 CHAPTER 2 INSTRUCTIONS CMP4S [Format] CMP4S [DS1-spec:] dst-string, [Seg-spec:] src-string CMP4S [Operation] [Operand] BCD string (IY, CL) BCD string (IX, CL) Decimal compare Compare Nibble String Mnemonic CMP4S Operand (dst, src) [DS1-spec : ] dst-string, [Seg-spec : ] src-string None [Flag] AC CY U V U P U S U Z [Description] Subtracts the packed BCD string addressed by the IX register from the packed BCD string addressed by the IY register. The result is not stored and only the flags are affected. The string length (number of BCD digits) is determined by the CL register (the number of digits is d if the contents of CL is d) in a range of 1 to 254 digits. The destination string must be always located in a segment specified by the DS1 register, and the segment cannot be overridden. Although the default segment register of the source string is the DS0 register, the segment can be overridden, and the string can be located in a segment specified by any segment register. The format of a packed BCD string is as follows. IX IY Byte offset +m Memory +CL Digit offset +4 +3 +2 +1 0 +1 +0 Caution The BCD string instruction always operates in units of an even number of digits. If an even number of digits is specified, therefore, the result of the operation and each flag operation are normal. If an odd number of digits is specified, however, an operation of an even number of digits, or an odd number of digits + 1, is executed. As a result, the result of the operation is an even number of digits and each flag indicates an even number of digits. To specify an odd number of digits, therefore, keep this in mind: Execute the BCD compare instruction, if the number of digits is odd, after clearing the high-order 4 bits of the most significant byte to "0". 59 CHAPTER 2 INSTRUCTIONS [Example] MOV IX, OFFSET VAR_1 MOV IY, OFFSET VAR_2 MOV CL, 4 CMP4S [Number of bytes] [Word format] 2 Mnemonic CMP4S Operand [DS1-spec : ] dst-string, [Seg-spec : ] src-string None Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 60 CHAPTER 2 INSTRUCTIONS CMPBK CMPBKB CMPBKW [Format] Block compare Compare Block Compare Block Byte Compare Block Word (repeat) CMPBK [Seg-spec:] src-block, [DS1-spec:] dst- block (repeat) CMPBKB (repeat) CMPBKW [Operation] [When W = 0] (IX) (IY) DIR = 0: IX IX + 1, IY IY + 1 DIR = 1: IX IX 1, IY IY 1 [When W = 1] (IX + 1, IX) (IY + 1, IY) DIR = 0: IX IX + 2, IY IY + 2 DIR = 1: IX IX 2, IY IY 2 [Operand] Mnemonic CMPBK CMPBKB CMPBKW Operand [Seg-spec : ] src-block, [DS1-spec : ] dst-block None [Flag] AC CY V P S Z [Description] Repeatedly subtracts the block addressed by the IY register from the block addressed by the IX register in byte or word units, and reflects the result on the flags. The IX and IY registers are automatically incremented (+1/+2) or decremented (1/2) for the next byte/word processing each time data of 1 byte/word has been processed. The direction of the block is determined by the status of the DIR flag. Whether data is processed in byte or word units is specified by the attribute of the operand when the CMPBK instruction is used. When the CMPBKB and CMPBKW instructions are used, the data is processed in byte and word units, respectively. The destination block must be always located in a segment specified by the DS1 register, and the segment cannot be overridden. On the other hand, although the default segment register of the source block is the DS0 register, the segment can be overridden, and the block can be located in a segment specified by any segment register. [Example] [Number of bytes] CMPBK BYTE_VAR1, BYTE_VAR2 1 61 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic CMPBK CMPBKB CMPBKW Operand [Seg-spec : ] src-block, [DS1-spec : ] dst-block None Operation code 7 6 5 4 3 2 1 0 1 0 1 0 0 1 1 W 62 CHAPTER 2 INSTRUCTIONS CMPM CMPMB CMPMW [Format] (repeat) CMPM [DS1-spec:] dst-block (repeat) CMPMB (repeat) CMPMW [Operation] [When W = 0] AL (IY) DIR = 0: IY IY + 1 DIR = 1: IY IY 1 [When W = 1] AW (IY + 1, IY) DIR = 0: IY IY + 2 DIR = 1: IY IY 2 [Operand] Block compare with accumulator Compare Multiple Compare Multiple Byte Compare Multiple Word Mnemonic CMPM CMPMB CMPMW Operand [DS1-spec : ] dst-block None [Flag] AC CY V P S Z [Description] Repeatedly subtracts the block addressed by the IY register from the value of the accumulator (AL/AW) in byte or word units, and reflects the result on the flags. The IY register is automatically incremented (+1/+2) or decremented (1/2) for the next byte/word processing each time data of 1 byte/word has been processed. The direction of the block is determined by the status of the DIR flag. Whether data is processed in byte or word units is specified by the attribute of the operand when the CMPM instruction is used. When the CMPMB and CMPMW instructions are used, the data is processed in byte and word units, respectively. The destination block must be always located in a segment specified by the DS1 register, and the segment cannot be overridden. [Example] MOV MOV MOV REPC REPNC REPZ AW, 5555H BW, 1000H IY, BW CMPM WORD PTR [IY] CMPMW CMPMB [Number of bytes] 1 63 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic CMPM CMPMB CMPMW Operand [DS1-spec : ] dst-block None Operation code 7 6 5 4 3 2 1 0 1 0 1 0 1 1 1 W 64 CHAPTER 2 INSTRUCTIONS CVTBD [Format] [Operation] CVTBD AH AL 0AH AL AL%0AH [Operand] Binary-to-unpacked decimal conversion Convert Binary to Decimal Mnemonic CVTBD None Operand [Flag] AC CY U U V U P S Z [Description] Converts the 8-bit binary number of the AL register into a 2- digit unpacked decimal number. As a result, the value of the AH register is replaced with the quotient resulting from dividing the value of the AL register by 10, and then the value of the AL register is replaced with the remainder resulting from the division. [Example] MOV AL, 30H CVTBD [Number of bytes] [Word format] 2 Mnemonic CVTBD None Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 65 CHAPTER 2 INSTRUCTIONS CVTBW [Format] [Operation] CVTBW When AL < 80H: AH 0 When AL 80H: AH FFH [Operand] Word sign extension Convert Byte to Word Mnemonic CVTBW None Operand [Flag] AC CY V P S Z [Description] Extends the sign of the byte in the AL register to the AH register. This instruction is useful for obtaining a double- length dividend (word) from a certain byte before executing byte division. [Example] MOV CVTBW MOV DIV AL, BUF1; BUF1 is byte variable DL, 60 DL [Number of bytes] [Word format] 1 Mnemonic CVTBW None Operand Operation code 7 6 5 4 3 2 1 0 1 0 0 1 1 0 0 0 66 CHAPTER 2 INSTRUCTIONS CVTDB [Format] [Operation] CVTDB AL AH 0AH + AL AH 0 [Operand] Unpacked decimal-to-binary conversion Convert Decimal to Binary Mnemonic CVTDB None Operand [Flag] AC CY U U V U P S Z [Description] Converts the 2-digit unpacked decimal number of the AH and AL registers into a 16-bit binary number. As a result, the value of the AL register is replaced with the sum of value of the AL register and the result of multiplying the value of the AH register by 10, and the value of the AH register is replaced with 0. [Example] MOV AW, [BW] CVTDB [Number of bytes] [Word format] 2 Mnemonic CVTDB None Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 67 CHAPTER 2 INSTRUCTIONS CVTWL [Format] [Operation] CVTWL When AW < 8000H: DW 0 When AW 8000H: DW FFFFH [Operand] Double word sign extension Convert Word to Long Word Mnemonic CVTWL None Operand [Flag] AC CY V P S Z [Description] Extends the sign of the word of the AW register to the DW register. This instruction is useful for obtaining a double-length (double word) dividend from a certain word before executing word division. [Example] MOV CVTWL DIV AW, BUFFER CW [Number of bytes] [Word format] 1 Mnemonic CVTWL None Operand Operation code 7 6 5 4 3 2 1 0 1 0 0 1 1 0 0 1 68 CHAPTER 2 INSTRUCTIONS DBNZ [Format] [Operation] DBNZ short-label CW CW 1 Where CW 0: PC PC + ext-disp8 [Operand] Conditional loop where CW 0 Decrement and Branch if Not Zero Mnemonic DBNZ Operand short-label [Flag] AC CY V P S Z [Description] Decrements the value of the CW register (1) and, if the value of the CW register is not zero as a result, loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC. Execution can branch in the segment where this instruction is placed and in an address range of 128 to +127 bytes. Execution goes on to the next instruction if the above condition is not satisfied. [Example] LP21: . . . SHL DBNZ AL, 1 LP21 ; LP21 = label [Number of bytes] [Word format] 2 Mnemonic DBNZ Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 0 0 1 0 disp8 69 CHAPTER 2 INSTRUCTIONS DBNZE [Format] [Operation] DBNZE short-label CW CW 1 Conditional loop where CW 0 and Z = 1 Decrement and Branch if Not Zero and Equal Where CW 0 and Z = 1: PC PC + ext-disp8 [Operand] Mnemonic DBNZE Operand short-label [Flag] AC CY V P S Z [Description] Decrements the value of the CW register (1) and, if the value of the CW register is not zero and the Z flag is set to 1 as a result, loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC. Execution can branch in the segment where this instruction is placed and in an address range of 128 to +127 bytes. Execution goes on to the next instruction if the above condition is not satisfied. [Example] LP20: . . . AND DBNZE AL, BL LP20 ; LP20 = label [Number of bytes] [Word format] 2 Mnemonic DBNZE Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 1 disp8 70 CHAPTER 2 INSTRUCTIONS DBNZNE [Format] [Operation] DBNZNE short-label CW CW 1 Conditional loop where CW 0 and Z = 0 Decrement and Branch if Not Zero and Not Equal Where CW 0: PC PC + ext-disp8 [Operand] Mnemonic DBNZNE Operand short-label [Flag] AC CY V P S Z [Description] Decrements the value of the CW register (1) and, if the value of the CW register is not zero and the Z flag is cleared as a result, loads the current PC value with an 8-bit displacement added (actually, sign-extended 16 bits) to the PC. Execution can branch in the segment where this instruction is placed and in an address range of 128 to +127 bytes. Execution goes on to the next instruction if the above condition is not satisfied. [Example] LP19: . . . AND DBNZNE AL, 0FFH SHORT LP19 ; LP19 = label [Number of bytes] [Word format] 2 Mnemonic DBNZNE Operand short-label Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 0 disp8 71 CHAPTER 2 INSTRUCTIONS DEC [Format] [Operation] [Operand] DEC dst dst dst 1 Mnemonic DEC reg8 mem reg16 Operand Decrement Decrement [Flag] AC CY V P S Z [Description] [Example] Decrements the contents of the destination operand (dst) (1). DEC BW DEC BP DEC IX DEC IY [Number of bytes] Mnemonic DEC reg8 mem reg16 Operand No. of bytes 2 2-4 1 [Word format] Mnemonic DEC reg8 mem Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 W mod 0 0 1 (disp-low) (disp-high) reg -- reg mem reg16 0 1 0 0 1 72 CHAPTER 2 INSTRUCTIONS DI [Format] [Operation] [Operand] DI IE 0 Disable maskable interrupt Disable Interrupt Mnemonic DI None Operand [Flag] AC CY V P S Z IE 0 [Description] Resets the IE flag to 0 and disables the maskable interrupt. This instruction does not disable the non-maskable interrupt request and software interrupt request. [Example] DI PUSH R [Number of bytes] [Word format] 1 Mnemonic DI None Operand Operation code 7 6 5 4 3 2 1 0 1 1 1 1 1 0 1 0 73 CHAPTER 2 INSTRUCTIONS DISPOSE [Format] [Operation] DISPOSE SP BP BP (SP + 1, SP) SP SP + 2 [Operand] Mnemonic DISPOSE None Operand Deletes a stack frame Dispose a Stack Frame [Flag] AC CY V P S Z [Description] This instruction releases one frame of the stack frame created by the PREPARE instruction. A pointer value indicating one frame before is loaded to the BP, and a pointer value indicating the lowest frame is loaded to the SP. [Example] [Number of bytes] [Word format] DISPOSE 1 Mnemonic DISPOSE None Operand Operation code 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 1 74 CHAPTER 2 INSTRUCTIONS DIV [Format] [Operand, operation] Mnemonic DIV Operand (dst) reg8 Operation Signed division Divide Signed DIV dst mem8 temp AW Where temp dst > 0 and temp dst 7FH or, where temp dst < 0 and temp dst > 0 7FH 1, AH temp%dst AL temp dst Where temp dst > 0 and temp dst > 7FH or, where temp dst < 0 and temp dst 0 7FH 1, quotient and remainder are undefined. TA (001H, 000H) TC (003H, 002H) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP + 1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA temp DW, AW Where temp dst > 0 and temp dst 7FFFH or, where temp dst < 0 and temp dst > 0 7FFFH 1, DW temp%dst AW temp dst Where temp dst > 0 and temp dst > 7FFFH or, where temp dst < 0 and temp dst 0 7FFFH 1, quotient and remainder are undefined. TA (001H, 000H) TC (003H, 002H) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP + 1, SP) PS PS TC SP SP 2, (SP + 1, SP) PC PC TA reg16 mem16 [Flag] AC CY U U V U P U S U Z U 75 CHAPTER 2 INSTRUCTIONS [Description] Where src = reg8 or src = mem8 Divides the value of the AW register by the contents of the destination operand (dst) with sign. The quotient is stored to the AL register, and the remainder is stored to the AH register. The maximum value of the positive quotient is +127 (7FH), and the minimum value is 127 (81H). If the quotient is positive and is greater than the maximum value, or if the quotient is negative and is less than the minimum value, vector 0 interrupt occurs (especially where src = 00H), and the quotient and remainder are undefined. If the quotient is not an integer, it is rounded to an integer, and the remainder has the same sign as the dividend. Where src = reg16 or src = mem16 Divides the values of the AW and DW registers by the contents of the destination operand (dst) with sign. The quotient is stored to the AW register, and the remainder is stored to the DW register. The maximum value of the positive quotient is +32767 (7FFFH), and the minimum value is 32767 (8001H). If the quotient is positive and is greater than the maximum value, or if the quotient is negative and is less than the minimum value, vector 0 interrupt occurs (especially where src = 0000H), and the quotient and remainder are undefined. If the quotient is not an integer, it is rounded to an integer, and the remainder has the same sign as the dividend. [Example] To divide 32-bit data DW:AW by contents of memory 0:50 MOV MOV MOV DIV BW, 0 DS0, BW IX, 50H DS0:WORD PTR [IX] [Number of bytes] Mnemonic DIV reg8 mem8 reg16 mem16 Operand No. of bytes 2 2-4 2 2-4 [Word format] Mnemonic DIV reg8 mem8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 mod 1 1 1 (disp-low) (disp-high) reg mem reg mem reg16 mem16 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 mod 1 1 1 (disp-low) (disp-high) 76 CHAPTER 2 INSTRUCTIONS DIVU [Format] [Operand, operation] Mnemonic DIVU Operand (dst) reg8 Operation Unsigned division Divide Unsigned DIVU dst mem8 temp AW Where temp dst FFH: AH temp%dst AL temp dst Where temp dst > FFH: TA (001H, 000H) TC (003H, 002H) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP + 1, SP) PS RS TC SP SP 2, (SP + 1, SP) PC PC TA temp DW, AW Where temp dst FFFFH: DW temp%dst AW temp dst Where temp dst > FFFFH: TA (001H, 000H) TC (003H, 002H) SP SP 2, (SP + 1, SP) PSW IE 0, BRK 0 SP SP 2, (SP + 1, SP) PS RS TC SP SP 2, (SP + 1, SP) PC PC TA reg16 mem16 [Flag] AC CY U U V U P U S U Z U 77 CHAPTER 2 INSTRUCTIONS [Description] Where src = reg8 or src = mem8 Divides the value of the AW register by the contents of the destination operand (dst) without sign. The quotient is stored to the AL register, and the remainder is stored to the AH register. If the quotient exceeds the capacity of the AL register (FFH), vector 0 interrupt occurs (especially where src = 00H), and the quotient and remainder are undefined. If the quotient is not an integer, it is rounded to an integer. Where src = reg16 or src = mem16 Divides the values of the AW and DW registers by the contents of the destination operand (dst) without sign. The quotient is stored to the AW register, and the remainder is stored to the DW register. If the quotient exceeds the capacity of the AW register (FFFFH), vector 0 interrupt occurs (especially where src = 0000H), and the quotient and remainder are undefined. If the quotient is not an integer, it is rounded to an integer. [Example] To divide 5 by 3 MOV MOV DIVU ; AH = 2 AW, 5 DL, 3 DL AL = 1 [Number of bytes] Mnemonic DIVU reg8 mem8 reg16 mem16 Operand No. of bytes 2 2-4 2 2-4 [Word format] Mnemonic DIVU reg8 mem8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 mod 1 1 0 (disp-low) (disp-high) reg mem reg mem reg16 mem16 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 mod 1 1 0 (disp-low) (disp-high) 78 CHAPTER 2 INSTRUCTIONS DS0: DS1: PS: SS: [Format] DS0: DS1: PS: SS: [Operation] [Operand] Segment override prefix Segment override prefix Data Segment 0 Data Segment 1 Program Segment Stack Segment Mnemonic DS0: DS1: PS: SS: None Operand [Flag] AC CY V P S Z [Description] When a memory operand is accessed for which segment override is enabled, specifies a segment register that is described as an operand and used. Even if this instruction is not directly described, segment override can be specified by the assembler if the ASSUME (assembler directive) is used. Caution The hardware interrupt (maskable interrupt and non-maskable interrupt) request and single-step break cannot be accepted between this instruction and the next instruction. [Example] [Number of bytes] [Word Format] MOV DW, DS1: [BW]; Default segment register is DS0 1 Mnemonic DS0: DS1: PS: SS: None Operand Operation code 7 6 5 4 3 2 1 0 0 0 1 sreg 1 1 0 79 CHAPTER 2 INSTRUCTIONS EI [Format] [Operation] [Operand] EI IE 1 Enables maskable interrupt Enable Interrupt Mnemonic EI None Operand [Flag] AC CY V P S Z IE 1 [Description] Sets the IE flag to 1 and enables the maskable interrupt. However, the interrupt is actually enabled when the single instruction following the EI instruction is executed. [Example] POP EI R [Number of bytes] [Word format] 1 Mnemonic EI None Operand Operation code 7 6 5 4 3 2 1 0 1 1 1 1 1 0 1 1 80 CHAPTER 2 INSTRUCTIONS EXT [Format] [Operation] EXT dst, src AW 16-bit field Extracts bit field Extract Bit Field Bit length Byte boundary Segment base (default DS0) 15 AW 0 0 [Operand] Mnemonic EXT Operand (dst, src) reg8, reg8' reg8, imm4 [Flag] AC CY U U V U P U S U Z U [Description] Loads bit field data of the bit length specified by the source operand (src) from a memory area determined by byte offset addressed by the IX register and the bit offset specified by the 8-bit register described as the first operand to the AW register. At this time, 0 is loaded to the high-order bits of the AW register. After completion of the transfer, the IX register and the 8-bit register specified by the first operand are automatically updated to indicate the next bit field, as follows: reg8 reg8 + src + 1 if reg8 > 15 then { reg8 reg8 16 IX IX + 2 } , , Bit offset (IX) Byte offset Memory 81 CHAPTER 2 INSTRUCTIONS The value of the 8-bit register of the first operand that specifies a bit offset (15 bits max.) must be 0 to 15. The value of the source operand (src) that specifies the bit length (16 bits max.) must be 0 to 15. 0 indicates a length of 1 bit and 15 indicates a length of 16 bits. The bit field data can straddle a byte boundary of memory. The default segment register for the bit field of the source is the DS0 register, and segments can be overridden. The data can be located in any segment that is specified by any segment register. Caution Clear the high-order 4 bits of reg8 or reg8' to 0. [Example] EXT CL, DL EXT CL, 8 [Number of bytes] Mnemonic EXT Operand reg8, reg8' reg8, imm4 No. of bytes 3 4 [Word format] Mnemonic EXT Operand reg8, reg8' Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 reg' reg reg8, imm4 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 reg imm4 82 CHAPTER 2 INSTRUCTIONS FPO1 [Format] (1) FPO1 fp-op (2) FPO1 fp-op, mem [Operand, operation] Format (1) Mnemonic FPO1 fp-op Operand Controls floating-point coprocessor Floating Point Operation 1 Operation No operation Format (2) Mnemonic FPO1 Operand fp-op, mem Operation Data bus (mem) [Flag] AC CY V P S Z [Description] Format (1): This instruction is used to control an externally connected floating-point coprocessor. When the CPU fetches this instruction, it executes nothing but lets the coprocessor perform processing. Format (2): This instruction is used to control an externally connected floating-point coprocessor. When the CPU fetches this instruction, it lets the coprocessor perform processing and, if necessary, executes only auxiliary processing (such as effective address calculation, physical address generation, and starting a memory read cycle). The CPU does not read the data on the data bus in the memory read cycle started by CPU. [Example] FPO1 FPO1 FPO1 FPO1 010101010B 0FFH 6, BYTE PTR [IX] 4, WORD_VAR [Number of bytes] Mnemonic FPO1 fp-op Operand No. of bytes 2 2-4 fp-op, mem 83 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic FPO1 fp-op fp-op, mem Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 1 X X X 1 1 Y Y Y Z Z Z 1 1 0 1 1 X X X mod Y Y Y (disp-low) (disp-high) mem 84 CHAPTER 2 INSTRUCTIONS FPO2 [Format] (1) FPO2 fp-op (2) FPO2 fp-op, mem [Operand, operation] Format (1) Mnemonic FPO2 fp-op Operand Controls floating-point coprocessor Floating Point Operation 2 Operation No operation Format (2) Mnemonic FPO2 Operand fp-op, mem Operation Data bus (mem) [Flag] AC CY V P S Z [Description] Format (1): This instruction is used to control an externally connected floating-point coprocessor. When the CPU fetches this instruction, it executes nothing but lets the coprocessor perform processing. Format (2): This instruction is used to control an externally connected floating-point coprocessor. When the CPU fetches this instruction, it lets the coprocessor perform processing and, if necessary, executes only auxiliary processing (such as effective address calculation, physical address generation, and starting a memory read cycle). The CPU does not read the data on the data bus in the memory read cycle started by CPU. [Example] FPO2 FPO2 FPO2 FPO2 010101010B 0FFH 0101B, BYTE PTR [IY] 1010B, WORD_VAR [Number of bytes] Mnemonic FPO2 fp-op Operand No. of bytes 2 2-4 fp-op, mem 85 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic FPO2 fp-op fp-op, mem Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 1 0 0 1 1 X 1 1 Y Y Y Z Z Z 0 1 1 0 0 1 1 X mod Y Y Y (disp-low) (disp-high) mem 86 CHAPTER 2 INSTRUCTIONS HALT [Format] [Operation] [Operand] HALT CPU Halt Halt Halt Mnemonic HALT None Operand [Flag] AC CY V P S Z [Description] Stops clock supply to the CPU and sets the standby mode. The standby mode is released by the following: Reset input Maskable interrupt request input Non-maskable interrupt request input [Example] [Number of bytes] [Word format] HALT 1 Mnemonic HALT None Operand Operation code 7 6 5 4 3 2 1 0 1 1 1 1 0 1 0 0 87 CHAPTER 2 INSTRUCTIONS IN [Format] [Operand, operation] Mnemonic IN Operand (dst, src) acc, imm8 acc, DW Data input from I/O device Input IN dst, src Operation [When W = 0] AL (imm8) [When W = 1] AH (imm8 + 1), AL (imm8) [When W = 0] AL (DW) [When W = 1] AH (DW + 1), AL (DW) [Flag] AC CY V P S Z [Description] Transfers the register contents of the I/O device specified by the source operand (src) to the accumulator (AL or AW register) specified by the destination operand (dst). [Example] To transfer contents of port address 0DAH to AL register MOV DW, 0DAH IN AL, DW [Number of bytes] Mnemonic IN acc, imm8 acc, DW Operand No. of bytes 2 1 [Word format] Mnemonic IN Operand acc, imm8 acc, DW Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 0 1 0 W 1 1 1 0 1 1 0 W imm8 -- 88 CHAPTER 2 INSTRUCTIONS INC [Format] [Operation] [Operand] INC dst dst dst + 1 Mnemonic INC reg8 mem reg16 Operand (dst) Increment Increment [Flag] AC CY V P S Z [Description] [Example] Increments the contents of the destination operand (dst) (+1). INC DW INC BP INC SP [Number of bytes] Mnemonic INC reg8 mem reg16 Operand No. of bytes 2 2-4 1 [Word format] Mnemonic INC reg8 mem Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1 W mod 0 0 0 (disp-low) (disp-high) reg -- reg mem reg16 0 1 0 0 0 89 CHAPTER 2 INSTRUCTIONS INM [Format] [Operation] Block transfer between I/O and memory Input Multiple (repeat) INM [DS1-spec:] dst-block, DW [When W = 0] (IY) (DW) DIR = 0: IY IY + 1 DIR = 1: IY IY 1 [When W = 1] (IY + 1, IY) (DW + 1, DW) DIR = 0: IY IY + 2 DIR = 1: IY IY 2 [Operand] Mnemonic INM Operand [DS1-spec : ] dst-block, DW [Flag] AC CY V P S Z [Description] Transfers the register contents of the I/O device addressed by the DW register to the memory addressed by the IY register. The number of times the data is repeatedly transferred is controlled by the REP instruction, a repeat prefix used in pairs with this instruction. When the data is repeatedly transferred, the contents of the DW register (address of the I/O device) are fixed, but the value of the IY register is automatically incremented (+1/+2) or decremented (1/2) to transfer the next byte/word each time 1byte/word data has been transferred. The direction of the block is determined by the status of the DIR flag. Whether data is transferred in byte or word units is determined by the attribute of the operand. The INM instruction is used with a repeat prefix, REP instruction. The destination block must be always located in a segment specified by the DS1 register and segments cannot be overridden. [Example] To load contents of port address 0DAH (byte data) to memory work area MOV MOV MOV MOV INM MOV MOV MOV MOV MOV REP AW, 0 DS1, AW IY, 50H DW, 0DAH DS1:BYTE PTR [IY], DW AW, 0 DS1, AW IY, 0 DW, 0DAH CW, 0FFH INM DS1: BYTE PTR [IY], DW To load contents of port address 0DAH (byte data) to memory 0:0 through 0:FFH 90 CHAPTER 2 INSTRUCTIONS [Number of bytes] [Word format] 1 Mnemonic INM Operand Operation code 7 6 5 4 3 2 1 0 [DS1-spec : ] dst-block, DW 0 1 1 0 1 1 0 W 91 CHAPTER 2 INSTRUCTIONS INS [Format] [Operation] INS dst, src 16-bit field AW Inserts bit field Insert Bit Field 15 AW 0 Byte boundary [Operand] Mnemonic INS Operand (dst, src) reg8, reg8' reg8, imm4 [Flag] AC CY U U V U P U S U Z U [Description] Of the 16-bit data of the AW register, transfers the low-order bit data of the length specified by the source operand (src) to a memory area that is determined by the byte offset addressed by the DS1 and IY registers and the bit offset specified by the 8- bit register described as the first operand. After the data has been transferred, the IY register and the 8- bit register specified by the first operand are automatically updated as follows to indicate the next bit field. reg reg8 + src + 1 if reg8 > 15 then { reg8 reg8 16 IY IY + 2 } 92 src dst Segment base (DS1) , , Bit length 0 Bit offset (IY) Byte offset Memory CHAPTER 2 INSTRUCTIONS The value of the 8-bit register of the first operand that specifies the bit offset (15 bits max.) must be 0 to 15. The value of the source operand (src) that specifies the bit length (16 bits max.) must be 0 to 15. 0 indicates a length of 1 bit and 15 indicates a length of 16 bits. The bit field data can straddle a byte boundary of memory. The bit field of the destination must be always located in a segment specified by the DS1 register, and segments can be overridden. Caution Clear the high-order 4 bits of reg8 or reg8' to 0. [Example] INS DL, CL INS DL, 12 [Number of bytes] Mnemonic INS Operand reg8, reg8' reg8, imm4 No. of bytes 3 4 [Word format] Mnemonic INS Operand reg8, reg8' Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 1 1 reg' reg -- reg8, imm4 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 0 reg imm4 93 CHAPTER 2 INSTRUCTIONS LDEA [Format] [Operation] [Operand] LDEA reg16, mem16 reg16 mem16 Loads effective address Load Effective Address Mnemonic LDEA Operand (dst, src) reg16, mem16 [Flag] AC CY V P S Z [Description] Loads an effective address (offset) generated by the second operand to a 16-bit generalpurpose register specified by the first operand. This instruction is used to set the first value of an operand address to a register that is automatically used by the TRANS instruction or primitive block transfer instruction to specify an operand. [Example] To load offset of effective address of procedure INT_PROC to AW register LDEA LDEA AW, INT_PROC AW, [BP] VAR01 + 2 [Number of bytes] [Word format] 2 to 4 Mnemonic LDEA Operand reg16, mem16 Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 0 1 mod (disp-low) reg (disp-high) mem 94 CHAPTER 2 INSTRUCTIONS LDM LDMB LDMW [Format] (repeat) LDM [Seg-spec:] src-block (repeat) LDMB (repeat) LDMW [Operation] [When W = 0] AL (IX) DIR = 0: IX IX + 1 DIR = 1: IX IX 1 [When W = 1] AW (IX + 1, IX) DIR = 0: IX IX + 2 DIR = 1: IX IX 2 [Operand] Mnemonic LDM LDMB LDMW Operand [Seg-spec : ] src-block None Block load Load Multiple Load Multiple Byte Load Multiple Word [Flag] AC CY V P S Z [Description] Repeatedly transfers the block addressed by the IX register to the accumulator (AL/AW) in byte or word units. The IX register is automatically incremented (+1/+2) or decremented (1/2) for the next byte/word processing each time data of 1 byte/word has been processed. The direction of the block is determined by the status of the DIR flag. Whether data is processed in byte or word units is specified by the attribute of the operand when the LDM instruction is used. When the LDMB and LDMW instructions are used, the data is processed in byte and word units, respectively. The default segment register of the source block is the DS0 register and segments can be overridden. The source block can be located in a segment specified by any segment register. [Example] REP LDM DS1: BYTE_VAR ; DS1 segment REP LDMB ; DS0 segment [Number of bytes] 1 95 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic LDM LDMB LDMW Operand [Seg-spec : ]src-block None Operation code 7 6 5 4 3 2 1 0 1 0 1 0 1 1 0 W 96 CHAPTER 2 INSTRUCTIONS MOV [Format] (1) MOV dst, src (2) MOV dst1, dst2, src [Operand, operation] Format (1) Mnemonic MOV Operand (dst, src) reg, reg' mem, reg reg, mem mem, imm reg, imm acc, dmem dmem, acc sreg, reg16 sreg, mem16 reg16, sreg mem16, sreg AH, PSW PSW, AH dst src Transfers data Move Operation [When W = 0] AL (dmem) [When W = 1] AH (dmem + 1), AL (dmem) [When W = 0] (dmem) AL [When W = 1] (dmem + 1) AH, (dmem) AL dst src AH S, Z, , AC, , P, , CY S, Z, , AC, , P, , CY AH Format (2) Mnemonic Operand (dst1, dst2, src) DS0, reg16, mem32 DS1, reg16, mem32 Operation reg16 (mem32) DS0 (mem32 + 2) reg16 (mem32) DS1 (mem32 + 2) [Flag] Where operand is PSW or AH AC CY V P S Z Other than left AC CY V P S Z 97 CHAPTER 2 INSTRUCTIONS [Description] Format (1): Transfers the contents of the source operand (src) specified by the second operand to the destination operand (dst) specified by the first operand. If the operands are AH, PSW, the S, Z, AC, P, and CY flags are transferred to the AH register. Bits 1, 3, and 5 of the AH register are undefined as a result. If the operands are PSW, AH, bits 2, 4, 6, and 7 of the AH register are transferred to the S, Z, AC, P, and CY flags of the PSW, respectively. Caution If dst = sreg or src = sreg, the hardware interrupt (maskable interrupt or non-maskable interrupt) request and single-step break cannot be accepted between this instruction and the next instruction. Format (2): Transfers the low-order 16 bits (offset word of 32-bit pointer variable) of the 32-bit memory addressed by the source operand (src) to a 16-bit register specified by destination operand 2 (dst2), and the high-order 16 bits (segment word) of the 32-bit memory to a segment register (DS0 or DS1 register) specified by destination operand 1 (dst1). [Example] To write 55H to memory 0:50H MOV MOV MOV MOV MOV AW, 0 DS1, AW IY, 50H DL, 55H DS1: [IY], DL [Number of Bytes] Mnemonic MOV reg, reg' mem, reg reg, mem Operand No. of bytes 2 2-4 mem, imm reg, imm acc, dmem dmem, acc sreg, reg16 sreg, mem16 reg16, sreg mem16, sreg DS0, reg16, mem32 DS1, reg16, mem32 AH, PSW PSW, AH 3-6 2, 3 3 2 2-4 2 2-4 1 98 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic MOV reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 W 1 1 1 0 0 0 1 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) mem mem reg' mem reg, mem 1 0 0 0 1 0 1 W mod (disp-low) mem, imm 1 1 0 0 0 1 1 W mod 0 0 0 (disp-low) imm8 or imm16-low (disp-high) imm16-high imm8 or imm16-low -- addr-low -- addr-low -- reg mem reg, imm 1 0 1 1 W imm16-high reg acc, dmem 1 0 1 0 0 0 0 W addr-high dmem, acc 1 0 1 0 0 0 1 W addr-high sreg, reg16 sreg, mem16 1 0 0 0 1 1 1 0 1 1 0 sreg 1 0 0 0 1 1 1 0 mod 0 sreg (disp-low) (disp-high) reg16, sreg mem16, sreg 1 0 0 0 1 1 0 0 1 1 0 sreg 1 0 0 0 1 1 0 0 mod 0 sreg (disp-low) (disp-high) reg (disp-high) reg (disp-high) -- -- reg mem DS0, reg16, mem32 1 1 0 0 0 1 0 1 mod (disp-low) mem DS1, reg16, mem32 1 1 0 0 0 1 0 0 mod (disp-low) mem AH, PSW PSW, AH 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 99 CHAPTER 2 INSTRUCTIONS MOVBK MOVBKB MOVBKW [Format] (repeat) MOVBK [DS1-spec:] dst-block, [Seg-spec:] src-block (repeat) MOVBKB (repeat) MOVBKW [Operation] [When W = 0] (IY) (IX) DIR = 0: IX IX + 1, IY IY + 1 DIR = 1: IX IX 1, IY IY 1 [When W = 1] (IY + 1, IY) (IX + 1, IX) DIR = 0: IX IX + 2, IY IY + 2 DIR = 1: IX IX 2, IY IY 2 [Operand] Block transfer Move Block Move Block Byte Move Block Word Mnemonic MOVBK MOVBKB MOVBKW Operand [DS1-spec : ] dst-block, [Seg-spec : ] src-block None [Flag] AC CY V P S Z [Description] Repeatedly transfers the block addressed by the IX register to the block addressed by the IY register in byte or word units. The IX and IY registers are automatically incremented (+1/+2) or decremented (1/2) for the next byte/word processing each time data of 1 byte/word has been processed. The direction of the block is determined by the status of the DIR flag. Whether data is processed in byte or word units is specified by the attribute of the operand when the MOVBK instruction is used. When the MOVBKB and MOVBKW instructions are used, the data is processed in byte and word units, respectively. The destination block must be always located in a segment specified by the DS1 register, and segments cannot be overridden. On the other hand, the default segment register of the source block is the DS0 register, but segments can be overridden, and the source block can be located in a segment specified by any segment register. [Example] MOVBK BYTE_VAR1, BYTE_VAR2 MOVBK WORD_VAR1, WORD_VAR2 [Number of bytes] 1 100 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic MOBK MOVBKB MOVBKW Operand [DS1-spec : ]dst-block, [Seg-spec : ] src-block None Operation code 7 6 5 4 3 2 1 0 1 0 1 0 0 1 0 W 101 CHAPTER 2 INSTRUCTIONS MUL [Format] (1) MUL src (2) MUL dst, src (3) MUL dst, src1, src2 [Operand, operation] Format (1) Mnemonic MUL reg8 Operand AW AL src Signed multiply Multiply Signed Operation AH = Sign extension of AL: CY 0, V 0 mem8 AH Sign extension of AL: CY 1, V 1 DW, AW AW src DW = Sign extension of AW: CY 0, V 0 mem16 DW Sign extension of AW: CY 1, V 1 reg16 Format (2) Mnemonic MUL Operand reg16, imm8 dst dst src Product 16 bits: CY 0, V 0 reg16, imm16 Product > 6 bits: CY 1, V 1 Operation Format (3) Mnemonic MUL Operand reg16, reg16', imm8 reg16, mem16, imm8 reg16, reg16', imm16 reg16, mem16, imm16 dst src1 x src2 Product 16 bits: CY 0, V 0 Product > 16 bits: CY 1, V 1 Operation [Flag] AC CY U V P U S U Z U 102 CHAPTER 2 INSTRUCTIONS [Description] Format (1): Where src = reg8 or src = mem8 Multiplies the value of the AL register by the source operand (src) with sign, and stores the double-length result to the AW register. If the upper half (AH register) of the result is not the sign extension of the lower half (AL register) at this time, the CY and V flags are set to 1. The AH register is an extension register. Where src = reg16 or src = mem16 Multiplies the value of the AW register by the source operand (src) with sign, and stores the double-length result to the AW and DW registers. If the upper half (DW register) of the result is not the sign extension of the lower half (AW register) at this time, the CY and V flags are set to 1. The DW register is an extension register. Format (2): Multiplies the destination operand (dst) by the source operand (src) with sign, and stores the result to the destination operand (dst). Format (3): Multiplies the first source operand (src1) by the second source operand (src2) with sign, and stores the result to the destination operand (dst). [Example] To multiply value of AW register by contents of memory 0:50H (word data) MOV BW, 0 MOV DS0, BW MOV IX, 50H MUL WORD PTR [IX] [Number of bytes] Mnemonic MUL reg8 mem8 reg16 mem16 Operand No. of bytes 2 2-4 2 2-4 3 4 3 3-5 4 4-6 reg16, imm8 reg16, imm16 reg16, reg16', imm8 reg16, mem16, imm8 reg16, reg16', imm16 reg16, mem16, imm16 103 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic MUL reg8 mem8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 mod 1 0 1 (disp-low) (disp-high) reg mem reg mem reg16 mem16 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 mod 1 0 1 (disp-low) (disp-high) reg -- reg im16-high reg -- reg (disp-high) -- reg imm16-high reg (disp-high) imm16-high reg16, imm8 0 1 1 0 1 0 1 1 1 1 imm8 reg' reg16, imm16 0 1 1 0 1 0 0 1 1 1 imm16-low reg' reg16, imm16', imm8 0 1 1 0 1 0 1 1 1 1 imm8 reg' reg16, mem16, imm8 0 1 1 0 1 0 1 1 mod (disp-low) imm8 mem reg16, imm16', imm16 0 1 1 0 1 0 0 1 1 1 imm16-low reg' reg16, mem16, imm16 0 1 1 0 1 0 0 1 mod (disp-low) imm16-low mem 104 CHAPTER 2 INSTRUCTIONS MULU [Format] [Operand, operation] Mnemonic MULU reg8 mem8 reg16 Operand (src) AW AL src Unsigned multiply Multiply Unsigned MULU src Operation DW, AW AW src DW = 0 : CY 0, V 0 DW 0 : CY 1, V 1 mem16 [Flag] AC CY U V P U S U Z U [Description] Where src = reg8 or src = mem8 Multiplies the value of the AL register by the source operand (src) without sign, and stores the double-length result to the AW register. If the upper half (AH register) of the result is not zero at this time, the CY and V flags are set to 1. The AH register is an extension register. Where src = reg16 or src = mem16 Multiplies the value of the AW register by the source operand (src) with sign, and stores the double-length result to the AW and DW registers. If the upper half (DW register) of the result is not zero at this time, the CY and V flags are set to 1. The DW register is an extension register. [Example] To multiply contents of AL register by contents of CL register MULU CL [Number of bytes] Mnemonic MULU reg8 mem8 reg16 mem16 Operand No. of bytes 2 2-4 2 2-4 105 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic MULU reg8 mem8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 mod 1 0 0 (disp-low) (disp-high) reg mem reg mem reg16 mem16 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 mod 1 0 0 (disp-low) (disp-high) 106 CHAPTER 2 INSTRUCTIONS NEG [Format] [Operation] [Operand] NEG dst dst dst + 1 Mnemonic NEG reg mem Operand (dst) 2's complement Negate [Flag] AC CY Note V P S Z Note CY = 1. However, CY = 0 if dst is 0 before execution. [Description] [Example] Takes 2's complement of the contents of the destination operand (dst). NEG DL NEG CW NEG IX NEG BP [Number of bytes] Mnemonic NEG reg mem Operand No. of bytes 2 2-4 [Word format] Mnemonic NEG reg mem Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 W 1 1 0 1 1 1 1 1 1 0 1 1 W mod 0 1 1 (disp-low) (disp-high) reg mem 107 CHAPTER 2 INSTRUCTIONS NOP [Format] [Operation] [Operand] NOP No operation Mnemonic NOP None Operand No operation No Operation [Flag] AC CY V P S Z [Description] [Example] [Number of bytes] [Word format] Executes nothing but consumes three clock cycles. NOP 1 Mnemonic NOP None Operand Operation code 7 6 5 4 3 2 1 0 1 0 0 1 0 0 0 0 108 CHAPTER 2 INSTRUCTIONS NOT [Format] [Operation] [Operand] NOT dst dst dst Logical negation Not Mnemonic NOT reg mem Operand (dst) [Flag] AC CY V P S Z [Description] Inverts the bit specified by the destination operand (dst) (logical negation), and stores the result to the destination operand (dst). [Example] NOT AL NOT CW NOT IX [Number of bytes] Mnemonic NOT reg mem Operand No. of bytes 2 2-4 [Word format] Mnemonic NOT reg mem Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 W 1 1 0 1 0 1 1 1 1 0 1 1 W mod 0 1 0 (disp-low) (disp-high) reg mem 109 CHAPTER 2 INSTRUCTIONS NOT1 [Format] (1) NOT1 dst, src (2) NOT2 dst [Operation] Inverts bit Not Bit Format (1): Bit n of dst (n is specified by src) Bit n of dst (n is specified by src) Format (2): dst dst [Operand] Format (1) Mnemonic NOT1 Operand (dst, src) reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 Format (2) Mnemonic NOT1 CY Operand (dst) [Flag] Format (1) AC CY V P S Z Format (2) AC CY V P S Z [Description] Format (1): Logically inverts bit n (n is the contents of the source operand (src) specified by the second operand) of the destination operand (dst) specified by the first operand, and stores the result to the destination operand (dst). If the operand is reg8, CL or mem8, CL, only the low-order 3 bits of the value of CL (0 to 7) are valid. If the operand is reg16, CL or mem16, CL, only the low-order 4 bits of the value of CL (0 to 15) are valid. If the operand is reg8, imm3, only the low-order 3 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem8, imm3, only the low-order 3 bits of the immediate data at the last byte position of the instruction are valid. If the operand is reg16, imm4, only the low-order 4 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem16, imm4, only the low-order 4 bits of the immediate data at the last byte position of the instruction are valid. Format (2): Logically negates the contents of the CY flag and then stores the result to the CY flag. 110 CHAPTER 2 INSTRUCTIONS [Example] IN AL, 0 NOT1 AL, 7 [Number of bytes] Mnemonic NOT1 reg8, CL mem8, CL reg16, CL Operand No. of bytes 3 3-5 3 3-5 4 4-6 4 4-6 1 mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 CY [Word format] Mnemonic NOT1 reg8, CL Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 reg -- mem8, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 mod 0 0 0 (disp-high) mem (disp-low) -- reg16, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 reg -- mem16, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 mod 0 0 0 (disp-high) mem (disp-low) -- reg8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 reg imm3 mem8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 mod 0 0 0 (disp-high) mem (disp-low) imm3 reg16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 reg imm4 mem16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 mod 0 0 0 (disp-high) mem (disp-low) imm4 -- CY 1 1 1 1 0 1 0 1 111 CHAPTER 2 INSTRUCTIONS OR [Format] [Operand, operation] Mnemonic OR Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm dst dst src Operation Logical sum Or OR dst, src [When W = 0] AL AL v imm8 [When W = 1] AW AW v imm16 [Flag] AC CY U 0 V 0 P S Z [Description] ORs the destination operand (dst) specified by the first operand with the source operand (src) specified by the second operand, and stores the result to the destination operand (dst). [Example] [Number of bytes] OR AW, WORD PTR [IX] Mnemonic OR reg, reg' mem, reg reg, mem reg, imm Operand No. of bytes 2 2-4 2-4 3, 4 3-6 2, 3 mem, imm acc, imm 112 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic OR reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 W 1 1 0 0 0 0 1 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 0 0 1 0 1 W mod (disp-low) reg, immNote 1 0 0 0 0 0 0 W 1 1 0 0 1 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 0 W mod 0 0 1 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 0 0 1 1 0 W imm16-high Note The following code may be generated depending on the assembler or compiler used. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 W 1 1 0 0 1 imm8 -- reg Even in this case, the instruction is executed normally. Note, however, that some emulators do not support a function to disassemble or assemble this instruction. 113 CHAPTER 2 INSTRUCTIONS OUT [Format] [Operand, operation] Mnemonic OUT Operand (dst, src) imm8, acc DW, acc Output data to I/O device Output OUT dst, src Operation [When W = 0] (imm8) AL [When W = 1] (imm8 + 1) AH, (imm8) AL [When W = 0] (DW) AL [When W = 1] (DW + 1) AH, (DW) AL [Flag] AC CY V P S Z [Description] Transfers the contents of the accumulator (AL or AW register) to a register of the I/O device specified by the destination operand (dst). [Example] To transfer contents of AL register to port address 0D8H MOV DW, 0D8H OUT DW, AL [Number of bytes] Mnemonic OUT imm8, acc DW, acc Operand No. of bytes 2 1 [Word format] Mnemonic OUT Operand imm8, acc DW, acc Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 0 1 1 W 1 1 1 0 1 1 1 W imm8 -- 114 CHAPTER 2 INSTRUCTIONS OUTM [Format] [Operation] Block transfer between memory and I/O Output Multiple (repeat) OUTM DW, [Seg-spec:] src-block [When W = 0] (DW) (IX) DIR = 0: IX IX + 1 DIR = 1: IX IX 1 [When W = 1] (DW + 1, DW) (IX + 1, IX) DIR = 0: IX IX + 2 DIR = 1: IX IX 2 [Operand] Mnemonic OUTM Operand DW, [Seg-spec : ] src-block [Flag] AC CY V P S Z [Description] Transfers the memory contents addressed by the IX register to the I/O device addressed by the DW register. The number of times the data is repeatedly transferred is controlled by the REP instruction, a repeat prefix used in pairs with this instruction. When the data is repeatedly transferred, the contents of the DW register (address of the I/O device) are fixed, but the value of the IX register is automatically incremented (+1/+2) or decremented (1/2) to transfer the next byte/word each time 1-byte/word data has been transferred. The direction of the block is determined by the status of the DIR flag. Whether data is transferred in byte or word units is determined by the attribute of the operand. The OUTM instruction is used with a repeat prefix, REP instruction. Although the default segment register of the source block is the DS0 register, segments can be overridden, and the source block can be located in a segment specified by any segment register. [Example] To transfer contents of memory 0:50H to port address 0D8H (byte data) MOV MOV MOV MOV OUTM MOV MOV MOV MOV MOV REP AW, 0 DS0, AW IX, 50H DW, 0D8H DW, DS0: WORD PTR [IX] AW, 0 DS0, AW IX, 0H DW, 0D8H CW, 0FFH OUTM DW, DS0:PTR [IX] To transfer contents of memory 0:0H through 0FFH to port address 0D8H (byte data) 115 CHAPTER 2 INSTRUCTIONS [Number of bytes] [Word format] 1 Mnemonic OUTM Operand DW, [Seg-spec : ] src-block Operation code 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 W 116 CHAPTER 2 INSTRUCTIONS POLL [Format] [Operation] [Operand] POLL POLL and wait Waits for floating-point coprocessor Poll and wait Mnemonic POLL None Operand [Flag] AC CY V P S Z [Description] Other than V33A and V53A Places the CPU in the wait status until the POLL pin becomes active (low). Caution The BUSLOCK instruction must not be placed immediately before this instruction. V33A and V53A With coprocessor connected : Places the CPU in the wait status until the CPBUSY pin becomes inactive (high level). Without coprocessor : Generates coprocessor non-existent interrupt (vector 7). At this time, the first byte of this instruction is saved to the stack as an address. Caution The BUSLOCK instruction must not be placed immediately before this instruction. [Example] [Number of bytes] [Word format] POLL 1 Mnemonic POLL None Operand Operation code 7 6 5 4 3 2 1 0 1 0 0 1 1 0 1 1 117 CHAPTER 2 INSTRUCTIONS POP [Word format] [Operand, operation] Mnemonic POP mem16 Operand (dst) SP SP + 2 Restore from stack Pop POP dst Operation (mem16) (SP 1, SP 2) reg16 sreg PSW R IY (SP + 1, SP) IX (SP + 3, SP + 2) BP (SP + 5, SP + 4) BW (SP + 9, SP + 8) DW (SP + 11, SP + 10) CW (SP + 13, SP + 12) AW (SP + 15, SP + 14) SP SP + 16 SP SP + 2 dst (SP 1, SP 2) [Flag] When dst = PSW AC CY R R V R P R S R Z R MD DIR IE BRK R R R R Remark The V33A and V53A does not have an MD flag. Other than above AC CY V P S Z [Description] Transfers the contents of the stack to the destination operand (dst) (however, the stack contents are not transferred to the PS if dst = sreg). Cautions 1. When dst = sreg, the hardware interrupt (maskable interrupt and nonmaskable interrupt) request and single-step break cannot be accepted between this instruction and the next instruction. 2. When dst = PSW, the MD flag is restored only in the write- enabled status, and is not affected in the write-disabled status (except the V33A and V53A). 3. If the PUSH and POP instructions are executed to the SP register in combination, the value of the SP register before instruction execution minus 2 is stored to the SP register. 118 CHAPTER 2 INSTRUCTIONS [Example] POP POP POP POP MOV AW BW IY SP BP, SP [Number of bytes] Mnemonic POP mem16 reg16 sreg PSW R Operand No. of bytes 2-4 1 1 [Word format] Mnemonic POP mem16 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 1 mod 0 0 0 (disp-low) (disp-high) reg -- -- -- -- mem reg16 sreg PSW R 0 1 0 1 1 0 0 0 sreg 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 119 CHAPTER 2 INSTRUCTIONS PREPARE [Format] [Operation] PREPARE imm16, imm8 (SP 1, SP 2) BP SP SP 2 Creates stack frame Prepare New Stack Frame After executing temp SP, executes the following operation "imm8-1" times when imm8 > 0: (SP 1, SP 2) (BP 1 BP 2) SP SP 2 BP BP 2 Then executes (SP 1, SP 2) temp SP SP 2 BP temp SP SP imm16 When imm8 = 1, repetitive operation 1 is not performed. When imm8 = 0, operations 1 and 2 are not performed. [Operand] 2 1 Then executes the following processing: Mnemonic PREPARE Operand imm16, imm8 [Flag] AC CY V P S Z [Description] This instruction is used to generate a "stack frame" necessary for high-level languages of block structure (such as Pascal and Ada). The stack frame includes a group of pointers indicating the variables that can be referenced from the procedure and an area of local variables. This instruction copies the frame pointer to allow securing of a local variable area and referencing global variables. The 16-bit immediate data described as the first operand specifies the size (in bytes units) of the area secured for local variables, and the 8-bit immediate data described as the second operand indicates the depth of the procedure block (this depth is called a lexical level). The base address of the frame created by this instruction is set to BP. First, BP is saved to the stack. This is to restore the BP of the procedure at the calling side when the procedure has been completed. Next, the frame pointer (saved BP) in a range in which it can be referenced from the called procedure is pushed to the stack. The range in which the frame pointer can be referenced is the value of the lexical level of that procedure minus 1. 120 CHAPTER 2 INSTRUCTIONS If the lexical level is greater than 1, the frame pointer of this instruction itself is also pushed to the stack. This is to copy the frame pointer of the procedure called by this procedure when the called procedure copies the frame pointer. Next, the value of a new frame pointer is set, and the area of local variables used for that procedure are secured on the stack. In other words, the SP is decremented by the number of the local variables. [Example] MOV MOV CALL PREPARE MOV ADD MOV [Number of Bytes] [Word format] Mnemonic PREPARE Operand imm16, imm8 SP, 60H BP, SP CHK 0006, 04 AW, [BP + 0FAH] AW, [BP + 0F8A] [BP + 0FCH], AW 4 Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 0 imm16-high imm16-low imm8 121 CHAPTER 2 INSTRUCTIONS PUSH [Word format] [Operand, operation] Mnemonic PUSH mem16 Operand (src) SP SP 2 Saves to stack Push PUSH src Operation (SP + 1, SP) (mem16 + 1, mem16) reg16 sreg PSW R temp SP (SP 1, SP 2) AW (SP 3, SP 4) CW (SP 5, SP 6) DW (SP 7, SP 8) BW (SP 9, SP 10) temp (SP 11, SP 12) BP (SP 13, SP 14) IX (SP 15, SP 16) IY SP SP 16 imm8 (SP 1, SP 2) sign extension of imm8 SP SP 2 imm16 (SP 1, SP 2) imm16 SP SP 2 SP SP 2 (SP + 1, SP) src [Flag] AC CY V P S Z [Description] Saves the contents of the source operand (src) to the stack. If 8-bit immediate data (imm8) is described as the operand, imm8 is sign-extended, and saved to the stack addressed by the SP as 16-bit data. [Example] PUSH DS0 PUSH SS PUSH DS1 122 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic PUSH mem16 reg16 sreg PSW R imm8 imm16 Operand No. of bytes 2-4 1 1 2 3 [Word format] Mnemonic PUSH mem16 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 mod 1 1 0 (disp-low) (disp-high) reg -- -- -- -- imm8 imm16-low -- mem reg16 sreg PSW R imm8 imm16 0 1 0 1 0 0 0 0 sreg 1 1 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 0 imm16-high 123 CHAPTER 2 INSTRUCTIONS REP REPE REPZ [Format] REP REPE REPZ [Operation] Repeat prefix where Z = 1 Repeat Repeat while Equal Repeat while Zero [When CW 0] PS: executes byte instruction of PC + 1 CW CW 1 When Z 1: PC PC + 2 When Z = 1: Re-executes [When CW = 0] PC PC + 2 [Operand] Mnemonic REP REPE REPZ None Operand [Flag] AC CY V P S Z [Description] Executes the block transfer/compare/I/O instruction of the subsequent byte and decrements the value of CW register (1) while CW 0. REP is used in combination with the MOVBK, LDM, STM, OUTM, or INTM instruction, and repeatedly performs processing while CW 0, regardless of the value of the Z flag. REPZ and REPE are used in combination with the CMPBK or CMPM instruction, and exits from a loop if Z 1 or if CW = 0 as a result of comparison by each block instruction. The CW register is checked before the block compare instruction is executed, i.e., immediately before the REP/REPE/REPEZ instruction is executed. Therefore, if the REP/REPE/REPEZ instruction is executed when CW = 0, the subsequent block compare instruction is never executed, and the next instruction is executed. The Z flag is checked as a result of executing the subsequent block compare instruction, and the content of this flag immediately before the REPE/REPZ instruction is executed for the first time is irrelevant. Caution The hardware interrupt (maskable interrupt) and non- maskable interrupt request and single-step break cannot be accepted between this instruction and the next instruction. [Example] REP MOVBKW REPZ CMPBKW [Number of bytes] 1 124 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic REP REPE REPZ None Operand Operation code 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 1 125 CHAPTER 2 INSTRUCTIONS REPC [Format] [Operation] REPC Repeat prefix where CY = 1 Repeat while Carry [When CW 0] PS: executes byte instruction of PC + 1 CW CW 1 When CY 1: PC PC + 2 When CY = 1: Re-executes [When CW = 0] PC PC + 2 [Operand] Mnemonic REPC None Operand [Flag] AC CY V P S Z [Description] Executes the block compare (CMPBK or CMPM) instruction of the subsequent byte and decrements the value of the CW register (1) while CW 0. If CY 1 as a result of executing the block compare instruction, execution exits from a loop. The CW register is checked before the block compare instruction is executed, i.e., immediately before the REPC instruction is executed. Therefore, if the REPC instruction is executed when CW = 0, the subsequent block compare instruction is never executed, and the next instruction is executed. The CY flag is checked as a result of executing the subsequent block compare instruction, and the content of this flag immediately before the REPC instruction is executed for the first time is irrelevant. Caution The hardware interrupt (maskable interrupt) and non-maskable interrupt request and single-step break cannot be accepted between this instruction and the next instruction. [Example] [Number of bytes] [Word format] REPC CMPBKW 1 Mnemonic REPC None Operand Operation code 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 126 CHAPTER 2 INSTRUCTIONS REPNC [Format] [Operation] REPNC Repeat prefix where CY = 0 Repeat while Not Carry [When CW 0] PS: executes byte instruction of PC + 1 CW CW 1 When CY 1: Re-executes When CY = 1: PC PC + 2 [When CW = 0] PC PC + 2 [Operand] Mnemonic REPNC None Operand [Flag] AC CY V P S Z [Description] Executes the block compare (CMPBK or CMPM) instruction of the subsequent byte and decrements the value of the CW register (1) while CW 0. If CY = 1 as a result of executing the block compare instruction, execution exits from a loop. The CW register is checked before the block compare instruction is executed, i.e., immediately before the REPNC instruction is executed. Therefore, if the REPNC instruction is executed when CW = 0, the subsequent block compare instruction is never executed, and the next instruction is executed. The CY flag is checked as a result of executing the subsequent block compare instruction, and the content of this flag immediately before the REPNC instruction is executed for the first time is irrelevant. Caution The hardware interrupt (maskable interrupt) and non- maskable interrupt request and single-step break cannot be accepted between this instruction and the next instruction. [Example] [Number of bytes] [Word format] REPNC CMPMB 1 Mnemonic REPNC None Operand Operation code 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 0 127 CHAPTER 2 INSTRUCTIONS REPNE REPNZ [Format] REPNE REPNZ [Operation] Repeat prefix where Z = 0 Repeat while Not Equal Repeat while Not Zero [When CW 0] PS: executes byte instruction of PC + 1 CW CW 1 When Z 1: Re-executes When Z = 1: PC PC + 2 [When CW = 0] PC PC + 2 [Operand] Mnemonic REPNE REPNZ None Operand [Flag] AC CY V P S Z [Description] Executes the block compare (CMPBK or CMPM) instruction of the subsequent byte and decrements the value of the CW register (1) while CW 0. If Z 0 or if CW = 0 as a result of executing the block compare instruction, execution exits from a loop. The CW register is checked before the block compare instruction is executed, i.e., immediately before the REPNE/REPNZ instruction is executed. Therefore, if the REPNE/ REPNZ instruction is executed when CW = 0, the subsequent block compare instruction is never executed, and the next instruction is executed. The Z flag is checked as a result of executing the subsequent block compare instruction, and the content of this flag immediately before the REPNC/REPNZ instruction is executed for the first time is irrelevant. Caution The hardware interrupt (maskable interrupt) and non-maskable interrupt request and single-step break cannot be accepted between this instruction and the next instruction. [Example] REPNE CMPMB REPNZ CMPBKW [Number of bytes] [Word format] 1 Mnemonic REPNE REPNZ None Operand Operation code 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 0 128 CHAPTER 2 INSTRUCTIONS RET [Format] (1) RET (2) RET pop-value [Operand, operation] To return from call in segment Mnemonic RET None Operand SP SP + 2 pop-value Return from subroutine Return from Procedure Operation PC (SP + 1, SP) PC (SP + 1, SP) SP SP + 2 SP SP + pop-value To return from call outside segment Mnemonic RET None Operand Operation PC (SP + 1, SP) PS (SP + 3, SP + 2) SP SP + 4 pop-value PC (SP + 1, SP) PS (SP + 3, SP + 2) SP SP + 4 SP SP + pop-value [Flag] AC CY V P S Z [Description] To return from call in segment Restores the PC from the stack. If pop-value is described as the operand, 16-bit popvalue is added to the SP (this is useful for skipping the value of SP by the number of unnecessary parameters if the parameters saved to the stack following the PC are unnecessary). The assembler automatically distinguishes this instruction from the RET instruction to return from a call outside a segment. To return from call outside segment Restores the PC and PS from the stack. If pop-value is described as the operand, 16bit pop-value is added to the SP (this is useful for skipping the value of SP by the number of unnecessary parameters if the parameters saved to the stack following the PC are unnecessary). The assembler automatically distinguishes this instruction from the RET instruction to return from a call in a segment. 129 CHAPTER 2 INSTRUCTIONS [Example] POP R RET [Number of bytes] Mnemonic RET None pop-value Operand No. of bytes 1 3 [Word format] To return from call in segment Mnemonic RET None pop-value Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 pop-value-high -- pop-value-low -- To return from call outside segment Mnemonic RET None pop-value Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 0 1 0 1 1 1 1 0 0 1 0 1 0 pop-value-high -- pop-value-low -- 130 CHAPTER 2 INSTRUCTIONS RETEM [except V33A and V53A] [Format] [Operation] RETEM PC (SP + 1, SP) PS (SP + 3, SP + 2) PSW (SP + 5, SP + 4) SP SP + 6 Disables MD from being written. [Operand] Return from emulation mode Return from Emulation Mnemonic RETEM None Operand [Flag] AC CY R R V R P R S R Z R MD DIR IE BRK R R R R [Description] When the RETEM instruction is executed in the emulation mode (this instruction is interpreted as an instruction of the PD8080AF), the CPU returns from interrupt service to the native mode by restoring the PS, PC, and PSW that have been saved by the BRKEM instruction. The content in the native mode saved by the BRKEM instruction (i.e., "1") is restored to the MD flag. As a result, the CPU enters the native mode. After the RETEM instruction has been executed, the MD flag is disabled from being written, and cannot be restored even if the RETI or POP PSW instruction is executed. [Example] [Number of bytes] [Word format] RETEM 2 Mnemonic RETEM None Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 131 CHAPTER 2 INSTRUCTIONS RETI [Format] [Operation] RETI PC (SP + 1, SP) PS (SP + 3, SP + 2) PSW (SP + 5, SP + 4) SP SP + 6 [Operand] Return from interrupt Return from Interrupt Mnemonic RETI None Operand [Flag] AC CY R R V R P R S R Z R MD DIR IE BRK R R R R Remark The V33A and V53A do not have an MD flag. [Description] Restores the contents of the stack to the PC, PS, and PSW. This instruction is used to return execution from interrupt service. Caution The MD flag is restored only in the write-enabled status, and is not affected in the write-disabled status (except the V33A and V53A). [Example] POP R RETI [Number of bytes] [Word format] Mnemonic RETI None Operand 1 Operation code 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 1 132 CHAPTER 2 INSTRUCTIONS RETXA [V33A, V53A only] [Format] [Operation] RETXA imm8 temp1 (imm8 4 + 1, imm8 4) temp2 (imm8 4 + 3, imm8 4 + 2) XA 0 PC temp1 PS temp2 [Operand] Return from extended address mode Return from Extended Address Mode Mnemonic RETXA imm8 Operand [Flag] AC CY V P S Z [Description] Releases the extended address mode. Transfers control to the address stored in the entry of the interrupt vector table specified by the instruction, and resets bit 0 (XA flag) of the XAM register (internal I/O address: FF80H) to 0. If this instruction is executed in the normal address mode, the vector table at the address of the normal address mode is read and then execution jumps to the address of this vector table. If this instruction is executed in the extended address mode, the vector table at the address of the extended address mode is read, the normal address mode is set, and then execution jumps to the address read first. The values of PC, PS, and PSW are not restored from the stack. [Example] [Number of bytes] [Word format] RETXA 0AH 3 Mnemonic RETXA imm8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 imm8 -- 133 CHAPTER 2 INSTRUCTIONS ROL [Format] [Operation] CY 15/7 0 Rotate left Rotate Left ROL dst, src [Operand] Mnemonic ROL Operand (dst, src) reg, 1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8 [Flag] When src = 1 AC CY V P S Z Others AC CY V U P S Z [Description] When src = 1 Shifts the contents of the destination operand (dst) specified by the first operand 1 bit to the left. The data of the MSB (bit 7 or 15) of dst is shifted to the LSB (bit 0) position, and is also transferred to the CY flag. If the MSB is affected, the V flag is set to 1; if not, the V flag is reset to 0. When src = CL or src = imm8 Shifts the contents of the destination operand (dst) specified by the first operand to the left the number of bits of the contents of the source operand (src) specified by the second operand. The data of the MSB (bit 7 or 15) of dst is shifted to the LSB (bit 0) position, and is also transferred to the CY flag. [Example] MOV [IX], BL ROL BYTE PTR [IX], 1 [Number of bytes] Mnemonic ROL reg, 1 mem, 1 reg, CL mem, CL reg, imm8 Operand No. of bytes 2 2-4 2 2-4 3 3-5 mem, imm8 134 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic ROL reg, 1 mem, 1 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 W 1 1 0 0 0 1 1 0 1 0 0 0 W mod 0 0 0 (disp-low) (disp-high) reg mem reg mem reg, CL mem, CL 1 1 0 1 0 0 1 W 1 1 0 0 0 1 1 0 1 0 0 1 W mod 0 0 0 (disp-low) (disp-high) reg, imm8 1 1 0 0 0 0 0 W 1 1 0 0 0 imm8 -- reg mem, imm8 1 1 0 0 0 0 0 W mod 0 0 0 (disp-low) imm8 (disp-high) -- mem 135 CHAPTER 2 INSTRUCTIONS ROL4 [Format] [Operation] dst ALL High-order 4 bits Low-order 4 bits Rotate nibble to left Rotate Nibble Left ROL4 dst [Operand] Mnemonic ROL4 reg8 mem8 Operand (dst) [Flag] AC CY V P S Z [Description] Rotates the contents of the destination operand (dst) 1 digit to the left via the low-order 4 bits (ALL) of the AL register, handling the contents of the destination operand as a 2-digit packed BCD. As a result, the high-order 4 bits of the AL register are not guaranteed. [Example] MOV AL, 24H ROL4 AL MOV AL, BYTE PTR [IX] ROL4 AL [Number of bytes] Mnemonic ROL4 reg8 mem8 Operand No. of bytes 3 3-5 [Word format] Mnemonic ROL4 reg8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 reg -- mem8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 mod 0 0 0 (disp-high) mem (disp-low) -- 136 CHAPTER 2 INSTRUCTIONS ROLC [Format] [Operation] CY 15/7 0 Rotate left with carry Rotate Left with Carry ROLC dst, src [Operand] Mnemonic ROLC Operand (dst, src) reg, 1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8 [Flag] When src = 1 AC CY V P S Z Others AC CY V U P S Z [Description] When src = 1 Shifts the contents of the destination operand (dst) specified by the first operand 1 bit to the left via the CY flag. The data of the MSB (bit 7 or 15) of dst is transferred to the CY flag, and the data of the CY flag is transferred to the LSB (bit 0). If the MSB is affected, the V flag is set to 1; if not, the V flag is reset to 0. When src = CL or src = imm8 Shifts the contents of the destination operand (dst) specified by the first operand to the left the number of bits of the contents of the source operand (src) specified by the second operand via the CY flag. The data of the MSB (bit 7 or 15) of dst is transferred to the CY flag, and the data of the CY flag is transferred to the LSB (bit 0). [Example] ROLC AL, 1 ROLC CL, 1 ROLC DW, 1 ROLC AW, 1 137 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic ROLC reg, 1 mem, 1 reg, CL mem, CL reg, imm8 Operand No. of bytes 2 2-4 2 2-4 3 3-5 mem, imm8 [Word format] Mnemonic ROLC reg, 1 mem, 1 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 W 1 1 0 1 0 1 1 0 1 0 0 0 W mod 0 1 0 (disp-low) (disp-high) reg mem reg mem reg, CL mem, CL 1 1 0 1 0 0 1 W 1 1 0 1 0 1 1 0 1 0 0 1 W mod 0 1 0 (disp-low) (disp-high) reg, imm8 1 1 0 0 0 0 0 W 1 1 0 1 0 imm8 -- reg mem, imm8 1 1 0 0 0 0 0 W mod 0 1 0 (disp-low) imm8 (disp-high) -- mem 138 CHAPTER 2 INSTRUCTIONS ROR [Format] [Operation] CY 15/7 0 Rotate right Rotate Right ROR dst, src [Operand] Mnemonic ROR Operand (dst, src) reg, 1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8 [Flag] When src = 1 AC CY V P S Z Others AC CY V U P S Z [Description] When src = 1 Shifts the contents of the destination operand (dst) specified by the first operand 1 bit to the right. The data of the LSB (bit 0) of dst is shifted to the MSB (bit 7 or 15) position, and is also transferred to the CY flag. If the MSB is affected, the V flag is set to 1; if not, the V flag is reset to 0. When src = CL or src = imm8 Shifts the contents of the destination operand (dst) specified by the first operand to the right the number of bits of the contents of the source operand (src) specified by the second operand. The data of the LSB (bit 0) of dst is shifted to the MSB (bit 7 or 15) position, and is also transferred to the CY flag. [Example] ROR AL, 3 ROR CW, 6 ROR IY, 2 139 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic ROR reg, 1 mem, 1 reg, CL mem, CL reg, imm8 Operand No. of bytes 2 2-4 2 2-4 3 3-5 mem, imm8 [Word format] Mnemonic ROR reg, 1 mem, 1 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 W 1 1 0 0 1 1 1 0 1 0 0 0 W mod 0 0 1 (disp-low) (disp-high) reg mem reg mem reg, CL mem, CL 1 1 0 1 0 0 1 W 1 1 0 0 1 1 1 0 1 0 0 1 W mod 0 0 1 (disp-low) (disp-high) reg, imm8 1 1 0 0 0 0 0 W 1 1 0 0 1 imm8 -- reg mem, imm8 1 1 0 0 0 0 0 W mod 0 0 1 (disp-low) imm8 (disp-high) -- mem 140 CHAPTER 2 INSTRUCTIONS ROR4 [Format] [Operation] dst ALL High-order 4 bits Low-order 4 bits Rotate nibble to right Rotate Nibble Right ROR4 dst [Operand] Mnemonic ROR4 reg8 mem8 Operand (dst) [Flag] AC CY V P S Z [Description] Rotates the contents of the destination operand (dst) 1 digit to the right via the low-order 4 bits (ALL) of the AL register, handling the contents of the destination operand as a 2-digit packed BCD. As a result, the high-order 4 bits of the AL register are not guaranteed. [Example] MOV MOV AL, 24H AL, BYTE PTR [IX] ROR4 AL ROR4 AL [Number of bytes] Mnemonic ROR4 reg8 mem8 Operand No. of bytes 3 3-5 [Word format] Mnemonic ROR4 reg8 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 1 0 0 0 reg -- mem8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 mod 0 0 0 (disp-high) mem (disp-low) -- 141 CHAPTER 2 INSTRUCTIONS RORC [Format] [Operation] CY 15/7 0 Rotate right with carry Rotate Right with Carry RORC dst, src [Operand] Mnemonic RORC Operand (dst, src) reg, 1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8 [Flag] When src = 1 AC CY V P S Z Others AC CY V U P S Z [Description] When src = 1 Shifts the contents of the destination operand (dst) specified by the first operand 1 bit to the right via the CY flag. The data of the LSB (bit 0) of dst is transferred to the CY flag, and the data of the CY flag is transferred to the LSB (bit 7 or 15). If the MSB is affected, the V flag is set to 1; if not, the V flag is reset to 0. When src = CL or src = imm8 Shifts the contents of the destination operand (dst) specified by the first operand to the right by the number of bits of the contents of the source operand (src) specified by the second operand via the CY flag. The data of the LSB (bit 0) of dst is transferred to the CY flag, and the data of the CY flag is transferred to the MSB (bit 7 or 15). [Example] RORC AL, 1 RORC BL, 1 RORC CW, 1 RORC IX, 1 142 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic RORC reg, 1 mem, 1 reg, CL mem, CL reg, imm8 Operand No. of bytes 2 2-4 2 2-4 3 3-5 mem, imm8 [Word format] Mnemonic RORC reg, 1 mem, 1 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 W 1 1 0 1 1 1 1 0 1 0 0 0 W mod 0 1 1 (disp-low) (disp-high) reg mem reg mem reg, CL mem, CL 1 1 0 1 0 0 1 W 1 1 0 1 1 1 1 0 1 0 0 1 W mod 0 1 1 (disp-low) (disp-high) reg, imm8 1 1 0 0 0 0 0 W 1 1 0 1 1 imm8 -- reg mem, imm8 1 1 0 0 0 0 0 W mod 0 1 1 (disp-low) imm8 (disp-high) -- mem 143 CHAPTER 2 INSTRUCTIONS SET1 [Format] (1) SET1 dst, src (2) SET1 dst [Operation] Format (1): Bit n of dst (n is specified by src) 1 Format (2): dst 1 [Operand] Format (1) Mnemonic SET1 Operand (dst, src) reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 Sets bit Set Bit Format (2) Mnemonic SET1 CY DIR Operand (dst) [Flag] Format (1) AC CY V P S Z Format (2) (when dst = CY) AC CY 1 V P S Z Format (2) (when dst = DIR) AC CY V P S Z DIR 1 144 CHAPTER 2 INSTRUCTIONS [Description] Format (1): Sets bit n (n is the contents of the source operand (src) specified by the second operand) of the destination operand (dst) specified by the first operand to 1, and stores the result to the destination operand (dst). If the operand is reg8, CL or mem8, CL, only the low-order 3 bits of the value of CL (0 to 7) are valid. If the operand is reg16, CL or mem16, CL, only the low-order 4 bits of the value of CL (0 to 15) are valid. If the operand is reg8, imm3, only the low-order 3 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem8, imm3, only the low-order 3 bits of the immediate data at the last byte position of the instruction are valid. If the operand is reg16, imm4, only the low-order 4 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem16, imm4, only the low-order 4 bits of the immediate data at the last byte position of the instruction are valid. Format (2): When dst = CY, sets the CY flag to 1. When dst = DIR, sets the DIR flag to 1. Also sets so that the index registers (IX and IY) are auto-decremented when the MOVBK, CMPBK, CMPM, LDM, STM, INM, or OUTM instruction is executed. [Example] MOV OUT CL, 4 0DAH, AL SET1 AL, CL [Number of bytes] Mnemonic SET1 reg8, CL mem8, CL reg16, CL Operand No. of bytes 3 3-5 3 3-5 4 4-6 4 4-6 1 1 mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 CY DIR 145 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic SET1 reg8, CL Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 0 0 0 reg -- mem8, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 mod 0 0 0 (disp-high) mem (disp-low) -- reg16, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 1 0 0 0 reg -- mem16, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 mod 0 0 0 (disp-high) mem (disp-low) -- reg8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 reg imm3 mem8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 mod 0 0 0 (disp-high) mem (disp-low) imm3 rg16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 0 0 0 reg imm4 mem16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 mod 0 0 0 (disp-high) mem (disp-low) imm4 -- -- CY DIR 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 146 CHAPTER 2 INSTRUCTIONS SHL [Format] [Operation] CY 15/7 0 0 Shift left Shift Left SHL dst, src [Operand] Mnemonic SHL Operand (dst, src) reg, 1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8 [Flag] When src = 1 AC CY U V P S Z Others AC CY U V U P S Z [Description] When src = 1 Shifts the contents of the destination operand (dst) specified by the first operand 1 bit to the left. Zero is shifted in to the the LSB (bit 0) position of dst, and the data of the MSB (bit 7 or 15) is set to the CY flag. The V flag is cleared if the sign bit (bit 7 or 15) is not affected after shifting. When src = CL or src = imm8 Shifts the contents of the destination operand (dst) specified by the first operand to the left the number of bits of the contents of the source operand (src) specified by the second operand. Zero is shifted in to the LSB (bit 0) position of dst each time the data is shifted, and the data of the MSB (bit 7 or 15) is set to the CY flag. [Example] IN SHL AW, 0C8H WORD PTR [IY], 12 MOV [IY], AW 147 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic SHL reg, 1 mem, 1 reg, CL mem, CL reg, imm8 Operand No. of bytes 2 2-4 2 2-4 3 3-5 mem, imm8 [Word format] Mnemonic SHL reg, 1 mem, 1 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 W 1 1 1 0 0 1 1 0 1 0 0 0 W mod 1 0 0 (disp-low) (disp-high) reg mem reg mem reg, CL mem, CL 1 1 0 1 0 0 1 W 1 1 1 0 0 1 1 0 1 0 0 1 W mod 1 0 0 (disp-low) (disp-high) reg, imm8 1 1 0 0 0 0 0 W 1 1 1 0 0 imm8 -- reg mem, imm8 1 1 0 0 0 0 0 W mod 1 0 0 (disp-low) imm8 (disp-high) -- mem 148 CHAPTER 2 INSTRUCTIONS SHR [Format] [Operation] CY 0 15/7 0 Shift right Shift Right SHR dst, src [Operand] Mnemonic SHR Operand (dst, src) reg, 1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8 [Flag] When src = 1 AC CY U V P S Z Others AC CY U V U P S Z [Description] When src = 1 Shifts the contents of the destination operand (dst) specified by the first operand 1 bit to the right. Zero is shifted in to the the MSB (bit 7 or 15) position of dst, and the data of the LSB (bit 0) is set to the CY flag. The V flag is cleared if the sign bit (bit 7 or 15) is not affected after shifting. When src = CL or src = imm8 Shifts the contents of the destination operand (dst) specified by the first operand to the right the number of bits of the contents of the source operand (src) specified by the second operand. Zero is shifted in to the MSB (bit 7 or 15) position of dst each time the data is shifted, and the data of the LSB (bit 0) is set to the CY flag. [Example] RCV: IN AL, 0DAH SHR AL, 3 BC RCV SHR CW, 8 149 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic SHR reg, 1 mem, 1 reg, CL mem, CL reg, imm8 Operand No. of bytes 2 2-4 2 2-4 3 3-5 mem, imm8 [Word format] Mnemonic SHR reg, 1 mem, 1 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 W 1 1 1 0 1 1 1 0 1 0 0 0 W mod 1 0 1 (disp-low) (disp-high) reg mem reg mem reg, CL mem, CL 1 1 0 1 0 0 1 W 1 1 1 0 1 1 1 0 1 0 0 1 W mod 1 0 1 (disp-low) (disp-high) reg, imm8 1 1 0 0 0 0 0 W 1 1 1 0 1 imm8 -- reg mem, imm8 1 1 0 0 0 0 0 W mod 1 0 1 (disp-low) imm8 (disp-high) -- mem 150 CHAPTER 2 INSTRUCTIONS SHRA [Format] [Operation] SHRA dst, src Arithmetic shift right Shift Right Arithmetic CY 15/7 0 [Operand] Mnemonic SHRA Operand (dst, src) reg, 1 mem, 1 reg, CL mem, CL reg, imm8 mem, imm8 [Flag] When src = 1 AC CY U V 0 P S Z Others AC CY U V U P S Z [Description] When src = 1 Arithmetically shifts the contents of the destination operand (dst) specified by the first operand 1 bit to the right. The original value is shifted in to the the MSB (bit 7 or 15) position of dst, and the sign is not affected after shifting. The data of the LSB (bit 0) is set to the CY flag. When src = CL or src = imm8 Shifts the contents of the destination operand (dst) specified by the first operand to the right the number of bits of the contents of the source operand (src) specified by the second operand. The original value is shifted in to the MSB (bit 7 or 15) of dst, and the sign is not affected after shifting. The data of the LSB (bit 0) is set to the CY flag. [Example] MOV MOV CL, 2 CL, 9 SHRA BL, CL SHRA DW, CL 151 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic SHRA reg, 1 mem, 1 reg, CL mem, CL reg, imm8 Operand No. of bytes 2 2-4 2 2-4 3 3-5 mem, imm8 [Word format] Mnemonic SHRA reg, 1 mem, 1 Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 W 1 1 1 1 1 1 1 0 1 0 0 0 W mod 1 1 1 (disp-low) (disp-high) reg mem reg mem reg, CL mem, CL 1 1 0 1 0 0 1 W 1 1 1 1 1 1 1 0 1 0 0 1 W mod 1 1 1 (disp-low) (disp-high) reg, imm8 1 1 0 0 0 0 0 W 1 1 1 1 1 imm8 -- reg mem, imm8 1 1 0 0 0 0 0 W mod 1 1 1 (disp-low) imm8 (disp-high) -- mem 152 CHAPTER 2 INSTRUCTIONS STM STMB STMW [Format] (repeat) STM [DS1-spec:] dst-block (repeat) STMB (repeat) STMW [Operation] [When W = 0] (IY) AL DIR = 0: IY IY + 1 DIR = 1: IY IY 1 [When W = 1] (IY + 1, IY) AW DIR = 0: IY IY + 2 DIR = 1: IY IY 2 [Operand] Block store Store Multiple Store Multiple Byte Store Multiple Word Mnemonic STM STMB STMW Operand [DS1-spec : ] dst-block None [Flag] AC CY V P S Z [Description] Repeatedly transfers the value of the AL or AW register to the block addressed by the IY register in byte or word units. The IY register is automatically incremented (+1/+2) or decremented (1/2) for the next byte/word processing each time data of 1 byte/word has been processed. The direction of the block is determined by the status of the DIR flag. Whether data is processed in byte or word units is specified by the attribute of the operand when the STM instruction is used. When the STMB and STMW instructions are used, the data is processed in byte and word units, respectively. The destination block must be always located in a segment specified by the DS1 register, and the segment cannot be overridden. [Example] REP STM DS1: WORD_VAR : DS1 segment REP STMB ; DS1 segment [Number of bytes] 1 153 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic STM STMB STMW Operand [DS1-spec : ] dst-block None Operation code 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 W 154 CHAPTER 2 INSTRUCTIONS SUB [Format] [Operand, Operation] Mnemonic SUB Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm dst dst src Operation Subtract Subtract SUB dst, src [When W = 0] AL AL imm8 [When W = 1] AW AW imm16 [Flag] AC CY V P S Z [Description] Subtracts the contents of the source operand (src) specified by the second operand from the contents of the destination operand (dst) specified by the first operand, and stores the result to the destination operand (dst). [Example] To subtract contents of memory 0:50H from contents of DL register, and store result to DL register MOV AW, 0 MOV DS0, AW MOV IX, 50H SUB DL, DS0:BYTE PTR [IX] [Number of bytes] Mnemonic SUB reg, reg' mem, reg reg, mem reg, imm Operand No. of bytes 2 2-4 2-4 3, 4 3-6 2, 3 mem, imm acc, imm 155 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic SUB reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 1 0 1 0 1 W 1 1 0 0 1 0 1 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 1 0 1 0 1 W mod (disp-low) reg, imm 1 0 0 0 0 0 s W 1 1 1 0 1 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 s W mod 1 0 1 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 1 0 1 1 0 W imm16-high 156 CHAPTER 2 INSTRUCTIONS SUB4S [Format] SUB4S [DS1-spec:] dst-string, [Seg-spec:] src-string SUB4S [Operation] [Operand] Decimal subtraction Subtract Nibble String BCD string (IY, CL) BCD string (IY, CL) BCD string (IX, CL) Mnemonic SUB4S Operand (dst, src) [DS1-spec : ] dst-string, [Seg-spec : ] src-string None [Flag] AC CY U V U P U S U Z [Description] Subtracts the packed BCD string addressed by the IX register from the packed BCD string addressed by the IY register, and stores the result to the string addressed by the IY register. The string length (number of BCD digits) is determined by the CL register (the number of digits is d if the contents of CL is d) in a range of 1 to 254 digits. The destination string must be always located in a segment specified by the DS1 register, the segment cannot be overridden. Although the default segment register of the source string is the DS0 register, the segment can be overridden, and the string can be located in a segment specified by any segment register. The format of a packed BCD string is as follows. Byte offset +m Memory +CL Digit offset +4 +3 +2 +1 0 +1 +0 IX IY Caution The BCD string instruction always operates in units of an even number of digits. If an even number of digits is specified, therefore, the result of the operation and each flag operation are normal. If an odd number of digits is specified, however, an operation of an even number of digits, or an odd number of digits + 1, is executed. As a result, the result of the operation is an even number of digits and each flag indicates an even number of digits. To specify an odd number of digits, therefore, keep this in mind: Execute the BCD subtraction instruction, if the number of digits is odd, after clearing the high-order 4 bits of the most significant byte to "0". If a borrow occurs as a result, the high-order 4 bits of the most significant bit is "9". 157 CHAPTER 2 INSTRUCTIONS [Example] MOV IX, OFFSET VAR_1 MOV IY, OFFSET VAR_2 MOV CL, 4 SUB4S [Number of bytes] [Word format] 2 Mnemonic SUB4S Operand [DS1-spec : ] dst-string, [Seg-spec : ] src-string None Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 158 CHAPTER 2 INSTRUCTIONS SUBC [Format] [Operand, Operation] Mnemonic SUBC Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm Subtraction with carry Subtract with Carry SUBC dst, src Operation dst dst src CY [When W = 0] AL AL + imm8 CY [When W = 1] AW AW imm16 CY [Flag] AC CY V P S Z [Description] Subtracts the contents of the source operand (src) specified by the second operand from the contents of the destination operand (dst) specified by the first operand, and stores the result to the destination operand (dst). [Example] [Number of bytes] SUBC DL, BYTE PTR [IX] Mnemonic SUBC reg, reg' mem, reg reg, mem reg, imm Operand No. of bytes 2 2-4 2-4 3, 4 3-6 2, 3 mem, imm acc, imm 159 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic SUBC reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 1 1 0 1 W 1 1 0 0 0 1 1 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 0 1 1 0 1 W mod (disp-low) reg, imm 1 0 0 0 0 0 s W 1 1 0 1 1 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 s W mod 0 1 1 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 0 1 1 1 0 W imm16-high 160 CHAPTER 2 INSTRUCTIONS TEST [Format] [Operand, operation] Mnemonic TEST Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm [When W = 0] AL ^ imm8 [When W = 1] AW ^ imm16 dst ^ src Operation Test Test TEST dst, src [Flag] AC CY U 0 V 0 P S Z [Description] ANDs the destination operand (dst) specified by the first operand with the source operand (src) specified by the second operand. The result is not stored anywhere, but the flags are affected. [Example] IN AL, 0D8H TEST AL, `A' [Number of bytes] Mnemonic TEST reg, reg' mem, reg reg, mem reg, imm Operand No. of bytes 2 2-4 3, 4 3-6 2, 3 mem, imm acc, imm 161 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic TEST reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 W 1 1 1 0 0 0 0 1 0 W mod (disp-low) reg' reg (disp-high) reg (disp-high) reg mem reg mem reg, mem 1 0 0 0 0 1 0 W mod (disp-low) reg, imm 1 1 1 1 0 1 1 W 1 1 0 0 0 imm8 or imm16-low imm16-high mem, imm 1 1 1 1 0 1 1 W mod 0 0 0 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 1 0 1 0 1 0 0 W imm16-high 162 CHAPTER 2 INSTRUCTIONS TEST1 [Format] [Operation] TEST1 dst, src When bit n of dst = 0 (n is specified by src): Z 1 When bit n of dst = 1 (n is specified by src): Z 0 [Operand] Tests bit Test Bit Mnemonic TEST1 Operand (dst, src) reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 [Flag] AC CY U 0 V 0 P U S U Z [Description] Sets the Z flag to 1 if bit n (n is the contents of the source operand (src) specified by the second operand) of the destination operand (dst) specified by the first operand; otherwise, resets the Z flag to 0. If the operand is reg8, CL or mem8, CL, only the low-order 3 bits of the value of CL (0 to 7) are valid. If the operand is reg16, CL or mem16, CL, only the low-order 4 bits of the value of CL (0 to 15) are valid. If the operand is reg8, imm3, only the low-order 3 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem8, imm3, only the low-order 3 bits of the immediate data at the last byte position of the instruction are valid. If the operand is reg16, imm4, only the low-order 4 bits of the immediate data at the fourth byte position of the instruction are valid. If the operand is mem16, imm4, only the low-order 4 bits of the immediate data at the last byte position of the instruction are valid. [Example] MOV IN CL, 01 AL, 0DAH TEST1 AL, CL; Tests bit 1 163 CHAPTER 2 INSTRUCTIONS [Number of bytes] Mnemonic TEST1 reg8, CL mem8, CL reg16, CL Operand No. of bytes 3 3-5 3 3-5 4 4-6 4 4-6 mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 [Word format] Mnemonic TEST1 reg8, CL Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 reg -- mem8, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 mod 0 0 0 (disp-high) mem (disp-low) -- 0 0 1 0 0 0 1 -- reg16, CL 0 0 0 0 1 1 1 1 0 1 1 0 0 0 reg mem16, CL 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 mod 0 0 0 (disp-high) mem (disp-low) -- reg8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 reg imm3 mem8, imm3 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 mod 0 0 0 (disp-high) mem (disp-low) imm3 reg16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0 0 reg imm4 mem16, imm4 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 mod 0 0 0 (disp-high) mem (disp-low) imm4 164 CHAPTER 2 INSTRUCTIONS TRANS TRANSB [Format] TRANS src-table TRANS TRANSB [Operation] [Operand] AL (BW + AL) Mnemonic TRANS src-table None TRANSB None Operand Transfers conversion table Translate Translate Byte [Flag] AC CY V P S Z [Description] Transfers 1 byte of the 256-byte conversion table addressed by the BW and AL registers to the AL register. At this time, the BW register indicates the first address of the table, and the AL register specifies an offset value within 256 bytes from the first address. [Example] [Number of bytes] [Word format] TRANS SIN_TBL 1 Mnemonic TRANS src-table None TRANSB None Operand Operation code 7 6 5 4 3 2 1 0 1 1 0 1 0 1 1 1 165 CHAPTER 2 INSTRUCTIONS XCH [Format] [Operation] [Operand] XCH dst, src dst src Exchanges data Exchange Mnemonic XCH Operand (dst, src) reg, reg' mem, reg reg, mem AW, reg16 reg16, AW [Flag] AC CY V P S Z [Description] Exchanges the contents of the destination operand (dst) specified by the first operand with those of the source operand (src) specified by the second operand. [Example] MOV AW, 100H MOV BW, 50H XCH AW, BW ; AW = 50H, BW = 100H [Number of bytes] Mnemonic XCH reg, reg' mem, reg reg, mem Operand No. of bytes 2 2-4 AW, reg16 reg16, AW 1 [Word format] Mnemonic XCH reg, reg' Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 W 1 1 1 0 0 0 0 1 1 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg reg -- -- mem reg' mem mem, reg reg, mem 1 0 0 0 0 1 1 W mod (disp-low) AW, reg16 reg16, AW 1 0 0 1 0 1 0 0 1 0 Remark The operation code of the XCH AW, AW is the same as that of the NOP instruction. 166 CHAPTER 2 INSTRUCTIONS XOR [Format] [Operand, operation] Mnemonic XOR Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm dst dst src Exclusive OR Exclusive Or XOR dst, src Operation [When W = 0] AL AL imm8 [When W = 1] AW AW imm16 [Flag] AC CY U 0 V 0 P S Z [Description] Exclusive-ORs the destination operand (dst) specified by the first operand with the source operand (src) specified by the second operand, and stores the result to the destination operand (dst). [Example] XOR CL, DL XOR CW, CW; Clears CW register XOR AW, DW [Number of bytes] Mnemonic XOR Operand (dst, src) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm No. of bytes 2 2-4 2-4 3, 4 3-6 2, 3 167 CHAPTER 2 INSTRUCTIONS [Word format] Mnemonic XOR reg, reg' mem, reg Operand Operation code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 W 1 1 0 0 1 1 0 0 0 W mod (disp-low) reg reg (disp-high) reg (disp-high) reg mem reg` mem reg, mem 0 0 1 1 0 0 1 W mod (disp-low) reg, immNote 1 0 0 0 0 0 0 W 1 1 1 1 0 imm8 or imm16-low imm16-high mem, imm 1 0 0 0 0 0 0 W mod 1 1 0 (disp-low) imm8 or imm16-low (disp-high) mem imm16-high imm8 or imm16-low -- acc, imm 0 0 1 1 0 1 0 W imm16-high Note The following code may be generated depending on the assembler or compiler used. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 W 1 1 1 1 0 imm8 -- reg Even in this case, the instruction is executed normally. Note, however, that some emulators do not support a function to disassemble or assemble this instruction. 168 CHAPTER 2 INSTRUCTIONS 2.2 Number of Instruction Execution Clocks Table 2-8 shows the number of execution clocks of and the number of times word transfer is executed by each instruction in the alphabetical order of the mnemonics. (1) Clocks The value indicated in the table is the time required for the execution unit to execute a given instruction and is based on the following condition. (a) This time does not include prefetch time, pre-decode time, and bus wait time. (b) It is assumed that the number of wait cycles for memory access is 0. Therefore, the number of clocks in one bus cycle is as follows: Other than V33A and V53A : 4 clocks V33A and V53A : 2 clocks (c) It is assumed that the number of wait cycles for I/O access is 0. (d) The primitive block transfer and primitive I/O instructions include the repeat prefix. (e) When an odd address is accessed in word units, two bus cycles are started. The number of clocks required for accessing an odd or even address is separately shown in the table. (f) The external data bus width is as follows: V20, V20HL, V40, V40HL V30, V30HL, V50, V50HL, V33A Note, : 8 bits V53ANote : 16 bits Note If the bus width is set to 16 bits by using the bus sizing function. To set the bus width to 8 bits, increase the bus cycle to access word data in an even address by two-fold. (g) The number of clocks of the V33A and V53A are shown in the normal address mode. (2) Word transfers "Word transfers" in the table indicates the number of words transferred, i.e., the number of times the word data (16 bits) generated as a result of executing a given instruction is accessed on the bus. By using this value, the number of instruction execution clocks when a wait state is inserted can be calculated as follows: When an even address is accessed : (Number of instruction execution clocks with 0 wait) + (Number of times of word transfer) (Number of wait statuses) When an odd address is accessed : (Number of instruction execution clocks with 0 wait) + (Number of times of word transfer) (Number of wait statuses) 2 169 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (1/15) Word Transfers ADD reg, reg' mem, reg 0 2 0 1 W Condition Address Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 2 0 1 Odd Even acc, imm ADD4SNote [DS1-spec : ] dst-string, [Seg-spec : ] src-string None ADDC reg, reg' mem, reg 0 0 2 0 1 Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 2 0 1 Odd Even acc, imm ADJ4A ADJ4S ADJBA ADJBS AND None None None None reg, reg' mem, reg 0 0 0 0 0 0 2 0 1 Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 2 0 1 Odd Even acc, imm BC short-label 0 0 When CY = 1 When CY = 0 BCWZ short-label 0 When CW 0 When CW = 0 4 14 4 5 13 4 18 26 11 15 4 3 3 7 7 2 16 24 4 18 26 11 15 19 m + 7 2 16 24 19 m + 7 2 16 24 16 11 15 11 4 18 26 18 4 3 3 7 7 2 16 24 16 11 15 11 4 18 26 18 4 14 4 5 13 4 14 4 5 13 4 15 23 10 14 4 3 3 7 7 2 13 21 4 15 23 10 14 19 m + 7 2 13 21 19 m + 7 2 13 21 13 10 14 10 4 15 23 15 4 3 3 7 7 2 13 21 13 10 14 10 4 15 23 15 4 14 4 5 13 18 m + 2 2 7 11 7 6 8 6 2 7 11 7 2 2 2 4 4 2 7 11 7 6 8 6 2 7 11 7 2 6 3 3 6 0 0 4 19 m + 7 4 18 26 11 15 V20,V20HL 2 16 24 V30,V30HL 2 16 24 16 11 15 11 4 18 26 18 4 19 m + 7 4 19 m + 7 4 15 23 10 14 Clocks V40,V40HL 2 13 21 V50,V50HL 2 13 21 13 10 14 10 4 15 23 15 4 19 m + 7 V33A,V53A 2 7 11 7 6 8 6 2 7 11 7 2 18 m + 2 Mnemonic Operand Note m: Number of BCD digits 1/2 170 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (2/15) Word Transfers BE short-label 0 W Condition Address V20,V20HL 14 4 4 14 4 14 4 14 14 4 14 4 14 4 14 4 4 14 4 14 14 4 4 14 4 14 4 14 4 14 14 4 4 14 13 12 11 Odd Even far-label memptr32 0 2 Odd Even 15 35 24 V30,V30HL 14 4 4 14 4 14 4 14 14 4 14 4 14 4 14 4 4 14 4 14 14 4 4 14 4 14 4 14 4 14 14 4 4 14 13 12 11 24 20 15 35 27 15 34 Clocks V40,V40HL 14 4 4 14 4 14 4 14 14 4 14 4 14 4 14 4 4 14 4 14 14 4 4 14 4 14 4 14 4 14 14 4 4 14 13 12 11 23 V50,V50HL 14 4 4 14 4 14 4 14 14 4 14 4 14 4 14 4 4 14 4 14 14 4 4 14 4 14 4 14 4 14 14 4 4 14 13 12 11 23 19 15 34 26 V33A,V53A 6 3 3 6 3 6 3 6 6 3 6 3 6 3 6 3 3 6 3 6 6 3 3 6 3 6 3 6 3 6 6 3 3 6 7 7 7 13 11 7 17 13 Mnemonic Operand When Z = 1 When Z = 0 BGE short-label 0 When S V = 1 When S V = 0 BGT short-label 0 When (S V) Z = 1 When (S V) Z = 0 BH short-label 0 When CY Z = 1 When CY Z = 0 BL short-label 0 When CY = 1 When CY = 0 When (S V) Z = 1 When (S V) Z = 0 BLE short-label 0 BLT short-label 0 When S V = 1 When S V = 0 BN short-label 0 When S = 1 When S = 0 BNC short-label 0 When CY = 1 When CY = 0 BNE short-label 0 When Z = 1 When Z = 0 BNH short-label 0 When CY Z = 1 When CY Z = 0 BNL short-label 0 When CY = 1 When CY = 0 BNV short-label 0 When V = 1 When V = 0 BNZ short-label 0 When Z = 1 When Z = 0 BP short-label 0 When S = 1 When S = 0 BPE short-label 0 When P = 1 When P = 0 BPO short-label 0 When P = 1 When P = 0 BR near-label short-label regptr16 memptr16 0 0 0 1 171 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (3/15) Word Transfers BRK 3 5 W Condition Address Odd Even imm8 (3) 5 Odd Even BRKEM imm8 5 Odd Even BRKV None (when V = 1) 5 Odd Even None (when V = 0) BRKXA BUSLOCK BV imm8 None short-label 5 2 0 0 When V = 1 When V = 0 BZ short-label 0 When Z = 1 When Z = 0 CALL near-proc 1 Odd Even regptr16 1 Odd Even memptr16 2 Odd Even far-proc 2 Odd Even memptr32 4 Odd Even CALLN imm8 5 Odd Even CHKIND reg16, mem32Note (when interrupt condition is satisfied) reg16, mem32 (when interrupt condition is not satisfied) CLR1 reg8, CL mem8, CL reg16, CL mem16, CL 0 0 0 2 Even Odd Even reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 0 0 0 2 Odd Even CY DIR 0 0 2 2 6 15 6 23 5 14 5 22 18 5 14 5 22 14 6 15 6 23 15 2 2 2 2 6 12 6 20 5 11 5 19 17 5 11 5 19 11 6 12 6 20 12 2 2 12 4 9 4 13 9 4 9 4 13 9 2 2 2 Even Odd 26 53-56 26 25 52-55 25 24-26 14 7 Odd 73-76 58 47 29 31 18 3 2 14 4 14 4 20 52 50 50 V20,V20HL 50 V30,V30HL 50 38 50 38 50 38 52 40 3 2 14 4 14 4 20 16 18 14 31 23 29 21 47 31 58 38 73-76 72-75 58 47 29 31 18 3 2 14 4 14 4 20 52 50 50 Clocks V40,V40HL 50 V50,V50HL 50 38 50 38 50 38 52 40 3 2 14 4 14 4 20 16 18 14 31 23 29 21 47 31 58 38 72-75 V33A,V53A 24 18 24 18 26 20 3 12 2 6 3 6 3 9 7 9 7 15 11 13 9 23 15 30-32 Mnemonic Operand Note The number of clocks differs depending on the timing at which the interrupt is accepted. 172 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (4/15) Word Transfers CMP reg, reg' mem, reg 0 1 0 1 W Condition Address Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 1 0 1 Odd Even acc, imm CMP4SNote 1 [DS1-spec : ] dst-string, [Seg-spec : ] src-string None CMPBKNote 2 [Sg-spec : ] src-block, [DS1-spec : ] dst-block 0 2 rep (2) 0 1 Odd, odd Odd, even Even, even CMPBKB Note 2 Mnemonic Operand Clocks V20,V20HL 2 11 15 V30,V30HL 2 11 15 11 11 15 11 15 11 4 13 17 4 13 17 13 4 19 m + 7 4 19 m + 7 4 19 m + 7 4 12 16 10 14 V40,V40HL 2 10 14 V50,V50HL 2 10 14 10 10 14 10 4 12 16 12 4 19 m + 7 V33A,V53A 2 6 8 6 6 8 6 2 6 8 6 2 14 m + 2 0 0 19 m + 7 19 m + 7 19 m + 7 19 m + 7 14 m + 2 7 + 14 rep(13) 7 + 14 rep(13) 7 + 14 rep(13) 7 + 14 rep(13) 12 rep 1(11) 7 + 22 rep(21) 7 + 22 rep(21) 7 + 22 rep(21) 7 + 22 rep(21) 16 rep 1(15) 7 + 18 rep(17) 7 + 14 rep(13) 7 + 18 rep(17) 14 rep 1(13) 7 + 14 rep(13) 12 rep 1(11) None None 2 rep (2) 2 rep (2) 0 1 Odd, odd Odd, even Even, even 7 + 14 rep(13) 7 + 14 rep(13) 7 + 14 rep(13) 7 + 14 rep(13) 12 rep 1(11) 7 + 22 rep(21) 7 + 22 rep(21) 7 + 22 rep(21) 7 + 22 rep(21) 16 rep 1(15) 7 + 18 rep(17) 7 + 14 rep(13) 7 + 18 rep(17) 14 rep 1(13) 7 + 14 rep(13) 12 rep 1(11) CMPBKWNote 2 CMPMNote 2 [DS1-spec : ] dst-block 1 rep (1) 0 1 Odd Even 7 + 10 rep(7) 7 + 10 rep(7) 7 + 10 rep(7) 7 + 10 rep(7) 10 rep 1(9) 7 + 14 rep(11) 7 + 14 rep(11) 7 + 14 rep(11) 7 + 14 rep(11) 12 rep 1(11) 7 + 10 rep(7) 7 + 10 rep(7) 10 rep 1(9) CMPMBNote 2 CMPMWNote 2 None None 1 rep 1 rep (1) 0 1 Odd Even 7 + 10 rep(7) 7 + 10 rep(7) 7 + 10 rep(7) 7 + 10 rep(7) 10 rep 1(9) 7 + 14 rep(11) 7 + 14 rep(11) 7 + 14 rep(11) 7 + 14 rep(11) 12 rep 1(11) 7 + 10 rep(7) 15 2 7 4, 5 13 5 14 15 2 7 4, 5 13 5 14 15 2 7 4, 5 13 5 14 7 + 10 rep(7) 10 rep 1(9) 15 2 7 4, 5 13 5 14 12 2 8 2 6 3 6 CVTBD CVTBW CVTDB CVTWLNote 3 DBNZ None None None None short-label 0 0 0 0 0 When CW 0 When CW = 0 DBNZE short-label 0 When CW 0 and Z = 1 Other than above 5 14 5 14 5 14 5 14 3 6 DBNZNE short-label 0 When CW 0 and Z = 0 Other than above 5 5 5 5 3 Notes 1. m: Number of BCD digits 1/2 2. ( ): Applicable to processing that is performed only once 3. The number of clocks differs depending on the value of data (except the V33A and V53A). 173 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (5/15) Word Transfers DEC reg8 mem 0 2 0 1 W Condition Address Odd Even reg16 DI DISPOSE None None 0 0 1 Odd Even DIVNote 1 reg8 mem8 reg16 mem16 0 0 0 1 Odd Even DIVU reg8 mem8 reg16 mem16 0 0 0 1 Odd Even DS0: DS1: EI EXTNote 2 None None None reg8, reg8' 0 0 0 1 or 2 Odd Even reg8, imm4 1 or 2 Odd Even FPO1 fp-op fp-op, mem 0 1 Odd Even FPO2 fp-op fp-op, mem 0 1 Odd Even HALT IN None acc, imm8 0 1 0 1 Odd EvenNote 3 acc,DW 1 0 1 Odd EvenNote 3 INC reg8 mem 0 2 0 1 Odd Even reg16 0 2 2 16 24 8 12 2 9 13 2 15 2 15 34-59 2 2 2 34-59 19 25 25 34 29-34 34-39 38-43 47-52 2 2 10 V20,V20HL 2 16 24 V30,V30HL 2 16 24 16 2 2 10 6 29-34 34-39 38-43 47-52 43-48 19 25 25 34 30 2 2 2 34-59 26-55 34-59 26-55 2 15 11 2 15 11 2 9 13 9 8 12 8 2 16 24 16 2 2 2 13 21 8 12 2 9 13 2 14 2 14 34-59 2 2 2 34-59 19 24 25 34 29-34 34-39 38-43 47-52 2 2 10 Clocks V40,V40HL 2 13 21 V50,V50HL 2 13 21 13 2 2 10 6 29-34 34-39 38-43 47-52 43-48 19 24 25 34 30 2 2 2 34-59 26-55 34-59 26-55 2 14 10 2 14 10 2 9 13 9 8 12 8 2 13 21 13 2 V33A,V53A 2 7 11 7 2 2 8 6 17 20 24 30 28 11 15 19 25 23 2 2 2 33-63 29-61 33-63 29-61 Cannot be defined Cannot be defined Cannot be defined Cannot be defined Cannot be defined Cannot be defined 2 5 7 5 5 7 5 2 7 11 7 2 Mnemonic Operand Notes 1. The number of clocks differs depending on the value of data (except the V33A and V53A). 2. The number of clocks differs depending on the value of data. 3. The number of clocks of the V50, V50HL, and V53A is the same as the number of execution clocks of an odd address because the bus cycle is started two times when the internal DMAU is accessed in word units. 174 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (6/15) Word Transfers INMNote 1 [DS1-spec : ] dst-block, DW 2 rep (2) W 0 1 Condition Address Odd, odd Odd, even Even, even INSNote 2 reg8, reg8' 2 or 4 Odd Even reg8, imm4 2 or 4 Odd Even LDEA LDMNote 1 reg16, mem16 [Seg-spec : ] src-block 0 1 rep (1) 0 1 Odd Even LDMBNote 1 LDMWNote 1 None None 1 rep(1) 1 rep (1) 0 1 Odd Even 7 + 9 rep (7) 4 7 + 9 rep (7) 35-133 35-133 V20,V20HL V30,V30HL Clocks V40,V40HL V50,V50HL V33A,V53A Note 3 Mnemonic Operand 9 + 8 rep (10) 9 + 8 rep (10) 9 + 8 rep (10) 9 + 8 rep (10) 9 + 16 rep (18) 9 + 16 rep (18) 9 + 16 rep (18) 9 + 16 rep (18) 9 + 12 rep (14) 9 + 8 rep (10) 35-133 31-117 35-133 31-117 4 7 + 9 rep (7) 4 7 + 9 rep (7) 35-133 35-133 9 + 12 rep (14) 9 + 8 rep (10) 35-133 31-117 35-133 31-117 4 7 + 9 rep (7) 39-77 37-69 39-77 37-69 2 2 + 3 rep (5) 7 + 13 rep (11) 7 + 13 rep (11) 7 + 13 rep (11) 7 + 13 rep (11) 2 + 5 rep (7) 7 + 9 rep (7) 7 + 9 rep (7) 7 + 9 rep (7) 7 + 9 rep (7) 7 + 9 rep (7) 2 + 3 rep (5) 2 + 3 rep (5) 7 + 13 rep (11) 7 + 13 rep (11) 7 + 13 rep (11) 7 + 13 rep (11) 2 + 5 rep (7) 7 + 9 rep (7) 7 + 9 rep (7) 2 + 3 rep (5) Notes 1. ( ): Applicable to processing that is performed only once 2. The number of clocks differs depending on the value of data. 3. The number of clocks of the V33A and V53A is as follows: Word Transfers INM [DS1-spec : ] dst-block, DW 2 rep (2) W 0 1 Condition Address Odd, odd Odd, even V33A 4 + 8 rep (12) 8 + 14 rep (14) If I/O address is odd: 8 + 8 rep (20) If memory address is odd: 4 + 10 rep (14) Even, even 4 + 8 rep (12) Clocks V53A 8 rep (8) 14 rep (14) If I/O address is odd: 12 rep (12) If memory address is odd: 10 rep (10) 8 rep (8) Mnemonic Operand 175 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (7/15) Word Transfers MOV reg, reg' mem, reg 0 1 0 1 W Condition Address Odd Even reg, mem 1 0 1 Odd Even mem, imm 1 0 1 Odd Even reg, imm acc, dmem 0 1 0 1 Odd Even dmem, acc 1 0 1 Odd Even sreg, reg16 sreg, mem16 0 1 Odd Even reg16, sreg mem16, sreg 0 1 Odd Even DS0, reg16, mem32 2 Odd Even DS1, reg16, mem32 2 Odd Even AH, PSW PSW, AH MOVBK Note Mnemonic Operand Clocks V20,V20HL 2 9 13 V30,V30HL 2 9 13 9 11 15 11 15 11 11 15 11 15 11 4 10 14 4 10 14 10 9 13 9 13 9 2 15 2 15 11 2 14 2 14 10 26 26 18 26 26 18 2 3 2 3 2 3 25 25 2 12 2 14 9 13 4 10 14 9 13 10 14 V40,V40HL 2 7 11 V50,V50HL 2 7 11 7 10 14 10 9 13 9 4 10 14 10 9 13 9 2 14 10 2 12 8 25 17 25 17 2 3 9 + 8 rep (9) V33A,V53A 2 3 5 3 5 7 5 3 5 3 2 5 7 5 3 5 3 2 7 5 2 5 3 14 10 14 10 2 2 6 rep (6) 10 rep (10) 8 rep (8) 6 rep (6) 6 rep (6) 10 rep (10) 8 rep (8) 6 rep (6) 0 0 2 rep (2) 0 1 Odd, odd Odd, even Even, even [DS1-spec : ] dst-block, [Seg-spec : ] src-block 11 + 8 rep (11) 11 + 8 rep (11) 9 + 8 rep (9) 11 + 16 rep (19) 11 + 16 rep (19) 9 + 16 rep (17) 9 + 16 rep (17) 11 + 12 rep (15) 11 + 8 rep (11) 11 + 8 rep (11) 11 + 8 rep (11) 9 + 8 rep (9) 9 + 12 rep (13) 9 + 8 rep (9) 9 + 8 rep (9) MOVBKBNote MOVBKWNote None None 2 rep (2) 2 rep (2) 0 1 Odd, odd Odd, even Even, even 11 + 16 rep (19) 11 + 16 rep (19) 9 + 16 rep (17) 9 + 16 rep (17) 11 + 12 rep (15) 11 + 8 rep (11) 9 + 12 rep (13) 9 + 8 rep (9) Note ( ): Applicable to processing that is performed only once. 176 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (8/15) Word Transfers MULNote reg8 mem8 reg16 mem16 0 0 0 1 W Condition Address Odd Even reg16, imm8 reg16, imm16 reg16, reg16', imm8 reg16, mem16, imm8 0 0 0 1 Odd Even reg16, reg16', imm16 reg16, mem16, imm16 0 1 Odd Even MULU Note Mnemonic Operand Clocks V20,V20HL 33-39 39-45 41-47 51-57 V30,V30HL 33-39 39-45 41-47 51-57 47-53 28-34 36-42 28-34 38-44 28-34 36-42 28-34 38-44 34-40 36-42 46-52 36-42 46-52 42-48 21, 22 27, 28 29, 30 21, 22 27, 28 29, 30 39, 40 35, 36 2 2 16 24 16 3 2 3 2 16 24 16 4 13 4 4 13 4 21 13 5 14 5 5 14 5 22 14 2 2 2 5 11 5 19 4 10 4 18 3 2 13 21 2 13 21 21, 22 26, 27 29, 30 38, 39 36-42 45-51 28-34 36-42 28-34 37-43 V40,V40HL 33-39 38-44 41-47 50-56 V50,V50HL 33-39 38-44 41-47 50-56 46-52 28-34 36-42 28-34 37-43 33-39 36-42 45-51 41-47 21, 22 26, 27 29, 30 38, 39 34, 35 2 13 21 13 3 2 13 21 13 4 10 4 18 10 5 11 5 19 11 2 V33A,V53A 8 12 12 18 16 12 12 12 18 16 12 18 16 8 12 12 18 16 2 7 11 7 3 2 7 11 7 4 9 4 13 9 4 9 4 13 9 2 reg8 mem8 reg16 mem16 0 1 0 1 Odd Even 39, 40 NEG reg mem 0 2 0 1 Odd Even 16 24 NOP NOT None reg mem 0 0 2 0 1 Odd Even 16 24 NOT1 reg8, CL mem8, CL reg16, CL mem16, CL 0 0 0 2 Odd Even 21 reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 0 0 0 2 Odd Even 22 CY 0 Note The number of clocks differs depending on the value of data (except the V33A and V53A). 177 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (9/15) Word Transfers OR reg, reg' mem, reg 0 2 0 1 W Condition Address Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 2 0 1 Odd Even acc, imm OUT imm8, acc 0 1 0 1 Odd EvenNote 3 DW, acc 1 0 1 Odd EvenNote 3 OUTMNote 1 DW, [Seg-spec : ] src-block 2 rep (2) 0 1 Odd, odd Odd, even Even, even POLLNote 2 None 0 2 + 5 poll 8 12 4 8 12 4 18 26 11 15 V20,V20HL 2 16 24 V30,V30HL 2 16 24 16 11 15 11 4 18 26 18 4 8 12 8 8 12 8 8 12 4 8 12 4 15 23 10 14 Clocks V40,V40HL 2 13 21 V50,V50HL 2 13 21 13 10 14 10 4 15 23 15 4 8 12 8 8 12 8 V33A,V53A 2 7 11 7 6 8 6 2 7 11 7 2 3 5 3 3 5 3 Note 4 Mnemonic Operand 9 + 8 rep (10) 9 + 8 rep (10) 9 + 8 rep (10) 9 + 8 rep (10) 9 + 16 rep (18) 9 + 16 rep (18) 9 + 16 rep (18) 9 + 16 rep (18) 9 + 12 rep (14) 9 + 8 rep (10) 2 + 5 poll 2 + 5 poll 9 + 12 rep (14) 9 + 8 rep (10) 2 + 5 poll 2 + 2 cpbusy Notes 1. ( ): Applicable to processing that is performed only once 2. poll: Number of times the POLL pin is sampled, cpbusy: Number of times the CPBUSY pin is sampled 3. The number of clocks of the V50, V50HL, and V53A is the same as the number of execution clocks of an odd address because the bus cycle is started two times when the internal DMAU is accessed in word units. 4. The number of clocks of the V33A and V53A is as follows: Word Transfers OUTM DW, [Seg-spec : ] src-block 2 rep (2) W 0 1 Condition Address Odd, odd Odd, even V33A 12 rep 6 (6) 22 rep 6 (16) If I/O address is odd: 20 rep 6 (10) If memory address is odd: 14 rep 6 (8) Even, even 12 rep 6 (6) Clocks V53A 8 rep 2 (6) 14 rep 2 (12) If I/O address is odd: 12 rep 2 (10) If memory address is odd: 10 rep 2 (8) 8 rep 2 (6) Mnemonic Operand 178 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (10/15) Word Transfers POP mem16 2 W Condition Address Odd Even reg16 1 Odd Even sreg 1 Odd Even PSW 1 Odd Even R 7 Odd Even PREPARE imm16, imm8 (When imm8 = 0) imm16, imm8 (When imm8 1) PS: PUSH None mem16 0 2 2 imm8 1 Odd Even Odd Even Odd Even reg16 1 Odd Even sreg 1 Odd Even PSW 1 Odd Even R 8 Odd Even imm8 1 Odd Even imm16 1 Odd Even REP REPC REPE REPNC REPNE REPNZ REPZ RET None None None None None None None None (call in segment) None (call outside segment) pop-value (call in segment) pop-value (call outside segment) RETEM None 3 2 1 2 0 0 0 0 0 0 0 1 Odd Even Odd Even Odd Even Odd Even Odd Even 39 32 24 29 2 2 2 2 2 2 2 19 12 11 67 12 12 12 2 26 16 75 12 12 12 V20,V20HL 25 V30,V30HL 25 17 12 8 12 8 12 8 75 43 16 12 16 75 12 12 12 Clocks V40,V40HL 24 V50,V50HL 24 16 12 8 12 8 12 8 75 43 16 12 V33A,V53A 9 5 7 5 7 5 7 5 38 22 15 Mnemonic Operand 23 + 16 (imm8-1) 21 + 16 (imm8-1) 21 + 16 (imm8-1) 21 + 16 (imm8-1) 17 + 12 (imm8-1) 19 + 8 (imm8-1) 2 26 18 12 8 12 8 12 8 67 35 11 7 12 8 2 2 2 2 2 2 2 19 15 29 21 24 20 32 24 39 27 39 32 24 29 2 2 2 2 2 2 2 19 10 9 65 10 10 10 2 23 17 + 8 (imm8-1) 2 23 15 10 6 10 6 10 6 65 33 9 5 10 6 2 2 2 2 2 2 2 19 15 29 21 24 20 32 24 39 27 15 + 8 (imm8-1) 2 9 5 5 3 5 3 5 3 36 20 5 3 5 3 2 2 2 2 2 2 2 12 10 16 12 12 10 16 12 179 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (11/15) Word Transfers RETI None 3 W Condition Address Odd Even RETXA ROLNote imm8 reg, 1 mem, 1 2 0 2 0 1 Odd Even reg, CL mem, CL 0 2 0 1 Odd Even reg, imm8 mem, imm8 0 2 0 1 Odd Even ROL4 reg8 mem8 ROLCNote reg, 1 mem, 1 0 0 0 2 0 1 Odd Even reg, CL mem, CL 0 2 0 1 Odd Even reg, imm8 mem, imm8 0 2 0 1 Odd Even ROR Note Mnemonic Operand Clocks V20,V20HL 39 V30,V30HL 39 27 6 16 24 6 16 24 16 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 13 28 6 16 24 13 28 6 16 24 16 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 6 6 16 24 16 7+n 7+n 19 + n 27 + n 19 + n 7+n 7+n 19 + n 27 + n 19 + n 17 32 17 32 17 29 7+n 16 + n 24 + n 7+n 16 + n 24 + n 6 13 21 7+n 16 + n 24 + n 7+n 16 + n 24 + n 13 25 6 13 21 7+n 16 + n 24 + n 7+n 16 + n 24 + n 6 13 21 V40,V40HL 39 V50,V50HL 39 27 6 13 21 13 7+n 16 + n 24 + n 16 + n 7+n 16 + n 24 + n 16 + n 13 25 6 13 21 13 7+n 16 + n 24 + n 16 + n 7+n 16 + n 24 + n 16 + n 6 13 21 13 7+n 16 + n 24 + n 16 + n 7+n 16 + n 24 + n 16 + n 17 29 V33A,V53A 19 13 12 2 7 11 7 2+n 6+n 10 + n 6+n 2+n 6+n 10 + n 6+n 9 15 2 7 11 7 2+n 6+n 10 + n 6+n 2+n 6+n 10 + n 6+n 2 7 11 7 2+n 6+n 10 + n 6+n 2+n 6+n 19 + n 6+n 13 19 reg, 1 mem, 1 0 2 0 1 Odd Even 16 24 reg, CL mem, CL 0 2 0 1 Odd Even 19 + n 27 + n reg, imm8 mem, imm8 0 2 0 1 Odd Even 19 + n 27 + n ROR4 reg8 mem8 0 0 Note n: Number of times of shift 180 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (12/15) Word Transfers RORCNote reg, 1 mem, 1 0 2 0 1 W Condition Address Odd Even reg, CL mem, CL 0 2 0 1 Odd Even reg, imm8 mem, imm8 0 2 0 1 Odd Even SET1 reg8, CL mem8, CL reg16, CL mem16, CL 0 0 0 2 Odd Even reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 0 0 0 2 Odd Even CY DIR SHLNote reg, 1 mem, 1 0 0 0 2 0 1 Odd Even reg, CL mem, CL 0 2 0 1 Odd Even reg, imm8 mem, imm8 0 2 0 1 Odd Even 7+n 19 + n 27 + n 7+n 19 + n 27 + n 2 2 6 16 24 5 14 5 22 4 13 4 21 7+n 19 + n 27 + n 7+n 19 + n 27 + n V20,V20HL 6 16 24 V30,V30HL 6 16 24 16 7+n 19 + n 27 + n 19 + n 7+n 19 + n 27 + n 19 + n 4 13 4 21 13 5 14 5 22 14 2 2 6 16 24 16 7+n 19 + n 27 + n 19 + n 7+n 19 + n 27 + n 19 + n 7+n 16 + n 24 + n 7+n 16 + n 24 + n 2 2 6 13 21 5 11 5 19 4 10 4 18 7+n 16 + n 24 + n 7+n 16 + n 24 + n Clocks V40,V40HL 6 13 21 V50,V50HL 6 13 21 13 7+n 16 + n 24 + n 16 + n 7+n 16 + n 24 + n 16 + n 4 10 4 18 10 5 11 5 19 11 2 2 6 13 21 13 7+n 16 + n 24 + n 16 + n 7+n 16 + n 24 + n 16 + n V33A,V53A 2 7 11 7 2+n 6+n 10 + n 6+n 2+n 6+n 10 + n 6+n 4 9 4 13 9 4 9 4 13 9 2 2 2 7 11 7 2+n 6+n 10 + n 6+n 2+n 6+n 10 + n 6+n Mnemonic Operand Note n: Number of times of shift 181 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (13/15) Word Transfers SHRNote 1 reg, 1 mem, 1 0 2 0 1 W Condition Address Odd Even reg, CL mem, CL 0 2 0 1 Odd Even reg, imm8 mem, imm8 0 2 0 1 Odd Even SHRANote 1 reg, 1 mem, 1 0 2 0 1 Odd Even reg, CL mem, CL 0 2 0 1 Odd Even reg, imm8 mem, imm8 0 2 0 1 Odd Even SS: STMNote 2 None [DS1-spec : ] dst-block 0 1 rep (1) 0 1 Odd Even STMBNote 2 STMW Note 2 Mnemonic Operand Clocks V20,V20HL 6 16 24 V30,V30HL 6 16 24 16 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 6 16 24 6 16 24 16 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 7+n 19 + n 27 + n 7+n 19 + n 27 + n 19 + n 2 2 2 7+n 16 + n 24 + n 7+n 16 + n 24 + n 6 13 21 7+n 16 + n 24 + n 7+n 16 + n 24 + n V40,V40HL 6 13 21 V50,V50HL 6 13 21 13 7+n 16 + n 24 + n 16 + n 7+n 16 + n 24 + n 16 + n 6 13 21 13 7+n 16 + n 24 + n 16 + n 7+n 16 + n 24 + n 16 + n 2 V33A,V53A 2 7 11 7 2+n 6+n 10 + n 6+n 2+n 6+n 10 + n 6+n 2 7 11 7 2+n 6+n 10 + n 6+n 2+n 6+n 10 + n 6+n 2 3 rep (3) 5 rep (5) 3 rep (3) 3 rep (3) 5 rep (5) 3 rep (3) 2 7 11 7 6 8 6 2 7 11 7 2 7 + 4 rep (7) 7 + 4 rep (7) 5 + 4 rep (5) 5 + 4 rep (5) 7 + 8 rep (11)7 + 8 rep (11) 5 + 8 rep (9) 5 + 8 rep (9) 7 + 4 rep (7) 5 + 4 rep (5) None None 1 rep (2) 1 rep (1) 0 1 Odd Even 7 + 4 rep (7) 7 + 4 rep (7) 5 + 4 rep (5) 5 + 4 rep (5) 7 + 8 rep (11)7 + 8 rep (11) 5 + 8 rep (9) 5 + 8 rep (9) 7 + 4 rep (7) 2 2 16 24 16 11 15 11 15 11 4 4 18 26 18 4 4 4 4 15 23 10 14 2 13 21 5 + 4 rep (5) 2 13 21 13 10 14 10 4 15 23 15 4 SUB reg, reg' mem, reg 0 2 0 1 Odd Even 16 24 reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 2 0 1 Odd Even 18 26 acc, imm 0 Notes 1. n: Number of times of shift 2. ( ): Applicable to processing that is performed only once 182 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (14/15) Word Transfers SUB4SNote [DS1-spec : ] dst-string, [Seg-spec : ] src-string None SUBC reg, reg' mem, reg 0 0 2 0 1 Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 2 0 1 Odd Even acc, imm TEST reg, reg' mem, reg 0 0 1 0 1 Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 1 0 1 Odd Even acc, imm TEST1 reg8, CL mem8, CL reg16, CL mem16, CL 0 0 0 0 1 Odd Even reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 0 0 0 1 Odd Even TRANS src-table None TRANSB None 1 1 1 9 9 9 4 9 4 13 4 3 8 3 12 4 11 15 10 14 4 2 10 14 4 18 26 11 15 19 m + 7 2 16 24 19 m + 7 2 16 24 16 11 15 11 4 18 26 18 4 2 10 14 10 10 14 10 4 11 15 11 4 3 8 3 12 8 4 9 4 13 9 9 9 9 9 9 9 4 8 4 12 4 3 7 3 11 4 10 14 9 13 4 2 9 13 4 15 23 10 14 19 m + 7 2 13 21 19 m + 7 2 13 21 13 10 14 10 4 15 23 15 4 2 9 13 9 9 13 9 4 10 14 10 4 3 7 3 11 7 4 8 4 12 8 9 9 9 18 m + 2 2 7 11 7 6 8 6 2 7 11 7 2 2 6 8 6 6 8 6 2 6 8 6 2 4 8 4 10 8 4 8 4 10 8 5 5 5 0 W Condition Address V20,V20HL 19 m + 7 V30,V30HL 19 m + 7 Clocks V40,V40HL 19 m + 7 V50,V50HL 19 m + 7 V33A,V53A 18 m + 2 Mnemonic Operand Note m: Number of BCD digits 1/2 183 CHAPTER 2 INSTRUCTIONS Table 2-8. Number of Instruction Execution Clocks (15/15) Word Transfers XCH reg, reg' mem, reg 0 2 0 1 W Condition Address Odd Even reg, mem 2 0 1 Odd Even AW, reg16 reg16, AW XOR reg, reg' mem, reg 0 0 0 2 0 1 Odd Even reg, mem 1 0 1 Odd Even reg, imm mem, imm 0 2 0 1 Odd Even acc, imm 0 4 4 18 26 11 15 3 3 2 16 24 16 24 V20,V20HL 3 16 24 V30,V30HL 3 16 24 16 16 24 16 3 3 2 16 24 16 11 15 11 4 18 26 18 4 4 4 15 23 10 14 3 3 2 13 21 13 21 Clocks V40,V40HL 3 13 21 V50,V50HL 3 13 21 13 13 21 13 3 3 2 13 21 13 10 14 10 4 15 23 15 4 V33A,V53A 3 8 12 8 8 12 8 3 3 2 7 11 7 6 8 6 2 7 11 7 2 Mnemonic Operand 184 APPENDIX A REGISTER CONFIGURATION A.1 General-Purpose Registers (AW, BW, CW, DW) Four 16-bit general-purpose registers are provided. These registers can be used not only as 16-bit registers but also as 8- bit registers (AH, AL, BH, BL, CH, CL, DH, and DL) with each register divided into the high-order and loworder 8 bits. Therefore, these registers are used as 8- or 16-bit registers with a variety of instructions such as transfer, arithmetic operation, and logical operation instructions. Also each register is used as a default register to process specific instructions as follows: AW : Word multiplication/division, word input/output, data exchange AL : Byte multiplication/division, byte input/output, BCD rotate, data exchange AH : Byte multiplication/division BW : Data exchange (table reference) CW : Loop control branch, repeat prefix CL : Shift instructions, rotate instructions, BCD operation DW : Word multiplication/division, indirect addressing input/output A.2 Segment Registers (PS, SS, DS0, DS1) The 16-bit V series divides the memory space into 64K-byte logical segments and can manage four segments at the same time (segment method). The first address of each segment is specified by the following segment registers: Program segment register (PS): Specifies base address of segment storing instructions Stack segment register (SS) : Specifies base address of segment performing stack operations Data segment 0 register (DS0) : Specifies base address of segment storing data Data segment 1 register (DS1) : Specifies base address of segment used by data transfer instruction as transfer destination of data A.3 Pointers (SP, BP) A pointer consists of two 16-bit registers (stack pointer (SP) and base pointer (BP)). Each register is used as a pointer that specifies a memory address and can also be referenced in instruction. When memory data is referenced, however, it is used as an index register. SP indicates the address in the stack segment that stores the latest data, and is used as a default register when the stack is manipulated. BP is used to restore data saved to the stack. A.4 Program Counter (PC) PC is a 16-bit binary counter that holds the offset information of the program memory address to be executed by the execution unit (EXU). The value of PC is automatically incremented (+1) each time the microprogram fetches an instruction byte from the instruction queue. When the branch, call, return, or break instruction is executed, a new location is loaded to PC. At this time, the value of PC is the same as that of the prefetch pointer (PFP). 185 APPENDIX A REGISTER CONFIGURATION A.5 Program Status Word (PSW) PSW consists of six status flags and four control flags. Status flags Overflow flag (V) Sign flag (S) Zero flag (Z) Auxiliary carry flag (AC) Parity flag (P) Carry flag (CY) Control flags Mode flag (MD)Note Direction flag (DIR) Interrupt enable flag (IE) Break flag (BRK) Note Except the V33A and V53A The status flag is automatically set to 1 or reset to 0 according to the result (data value) of executing an instruction. The CY flag is directly set, reset, or inverted by an instruction. The control flag is set or reset by an instruction to control the operation of the CPU. The IE and BRK flags are reset when interrupt service is started. Only the MD flag is set to 1 by RESET input, and all the other flags are reset to 0. PSW is manipulated in byte or word units by the following processing. If it is manipulated in byte units, only the low-order 8 bits (including the status flags except the V flag) are manipulated. Figure A-1. PSW Configuration 15 M D Note 14 13 1 1 12 1 11 V 10 D I R 9 I E 8 B R K 7 S 6 Z 5 0 4 A C 3 0 2 P 1 1 0 C Y Note The V33A and V53A is not provided with the MD flag. Bit 15 of PSW is fixed to 1. Bits 0 through 7 can be stored to or restored from AH by the MOV instruction. All the bits of PSW are saved to the stack when an interrupt occurs or when the call instruction is executed, and are restored from the stack by the return instruction (RETI or RETEM)Note. In addition, PSW can also be saved to or restored from the stack by the PUSH PSW or POP PSW instructionNote. Note The MD flag may be in the write-enabled or write-disabled status. In the write-disabled status, the MD flag is not restored from the stack but retains the current status even if the RETI or POP PSW instruction is executed. The MD flag is set in the write-disabled status by the reset operation and RETEM instruction, and is enabled by the BRKEM instruction. 186 APPENDIX A REGISTER CONFIGURATION Each flag is placed in the following status when each instruction is executed. (1) Carry flag (CY) (a) Binary addition/subtraction When a byte operation is executed, and if a carry or borrow occurs from bit 7 of the result of the operation, the CY flag is set; otherwise, it is reset. If a carry or borrow occurs from bit 15 of the result of executing a word operation, the CY flag is set; otherwise, it is reset. (b) Logical operation The CY flag remains reset regardless of the result. (c) Binary multiplication If AH is 0 as a result of executing an unsigned byte operation, the CY flag is reset; otherwise it is set. If AH sign-extends AL as a result of executing a signed byte operation, the CY flag is reset; otherwise, it is set. If DW is 0 as a result of executing an unsigned word operation, the CY flag is reset; otherwise, it is set. If DW sign-extends AW as a result of executing signed word operation, the CY flag is reset; otherwise, it is set. When an 8-bit immediate operation is executed, and if the product is within 16 bits, the CY flag is reset; if the product exceeds 16 bits, it is set. (d) Binary division Undefined (e) Shift/rotate If a shift or rotate operation including the CY flag is executed, and if the bit shifted to the CY flag is 1, the CY flag is set; otherwise, it is reset. (2) Parity flag (P) (a) Binary addition/subtraction, logical operation, shift If the number of bits that are 1 of the low-order 8 bits of the result of an operation is even, the parity flag is set; if the number of bits that are 1 is odd, the P flag is reset. If the result is all 0, the P flag is set. (b) Binary multiplication/division Undefined 187 APPENDIX A REGISTER CONFIGURATION (3) Auxiliary carry flag (AC) (a) Binary addition/subtraction The AC flag is set if a carry from the low-order 4 bits to the high-order 4 bits or a borrow from the highorder 4 bits to the low-order 4 bits occur as a result of a byte operation; otherwise, it is reset. When a word operation is executed, the AC flag is set or reset according to the status of the low-order byte. (b) Logical operation, binary multiplication/division, shift/rotate Undefined (4) Zero flag (Z) (a) Binary addition/subtraction, logical operation, shift/rotate If all the 8 bits of the result of a byte operation are zero, or if all the 16 bits of the result of a word operation are zero, the zero flag is set; otherwise, it is reset. (b) Binary multiplication/division Undefined (5) Sign flag (S) (a) Binary addition/subtraction, logical operation, shift/rotate If bit 7 of the result of a byte operation is 1, the sign flag is set; otherwise, it is reset. If bit 15 of the result of a word operation is 1, the sign flag is set; otherwise, it is reset. (b) Binary multiplication/division Undefined (6) Overflow flag (V) (a) Binary addition/subtraction If carries from bits 7 and 6 are different as a result of a byte operation, the overflow flag is set; otherwise, it is reset. If carries from bits 15 and 14 are different as a result of a word operation, the V flag is set; otherwise it is reset. (b) Binary multiplication If AH is 0 as a result of an unsigned byte operation, the V flag is set; if AH is other than 0, the flag is reset. If AH sign-extends AL as a result of a signed byte operation, the V flag is reset; otherwise, it is reset. If DW is 0 as a result of an unsigned word operation, the V flag is reset; if DW is other than 0, it is set. If DW sign-extends AW as a result of a signed word operation, the V flag is reset; otherwise, it is set. If the product resulting from an 8-bit immediate operation is within 16 bits, the V flag is reset; if the product exceeds 16 bits, it is set. (c) Binary division The V flag is reset. 188 APPENDIX A REGISTER CONFIGURATION (d) Logical operation The V flag is reset. (e) Shift/rotate When a left 1-bit shift/rotate operation is executed, the V flag is set or reset as follows according to the result of the operation. CY = most significant bit: reset CY most significant bit: set When a right 1-bit shift/rotate operation is executed, the V flag is set or reset as follows according to the result of the operation. Most significant bit = second most significant bit: reset Most significant bit second most significant bit: set The V flag is undefined if a multi-bit shift/rotate operation is executed. (7) Break flag (BRK) This flag can be set by a memory manipulation instruction only when it is saved to the stack as a part of PSW. After the BRK flag has been set and restored from the stack to PSW, setting the BRK flag is effective. Once the BRK flag has been set, and when one instruction is executed, a software interrupt (interrupt vector 1) automatically occurs, and one instruction can be traced at a time. (8) Interrupt enable flag (IE) This flag is set by the EI instruction to enable the INT interrupt, and is reset by the DI instruction to disable the INT interrupt. (9) Direction flag (DIR) This flag is set by the SET1 DIR instruction and is reset by the CLR1 DIR instruction. When the DIR flag is set, and if a block transfer/input/output instruction is executed, the processing is performed from the high-order address to the low-order address. If the DIR flag is reset, the processing is performed from the low-order address to the high-order address. (10) Mode flag (MD) (except V33A and V53A) This flag is set by RESET input and sets the CPU in the native mode. It is reset by the BRKEM instruction to set the CPU in the emulation mode. The MD flag is also set by the CALLN and RETEM instructions to set the CPU in the native mode. The RESET input and RETEM instruction disables the MD flag from being written. As a result, the MD flag is not restored even if the RETI or POP PSW instruction is executed. The BRKEM instruction enables writing the MD flag. 189 APPENDIX A REGISTER CONFIGURATION A.6 Index Registers (IX, IY) These two index registers are 16-bit registers. Each register can be referenced in an instruction, and is also used as an index register to generate effective address when memory data is referenced. Moreover, each register has a special role as follows when a specific instruction processing is performed. IX : Source operand address register for block data manipulation instruction Base register for variable-length bit field manipulation instruction Source operand address register for BCD string operation instruction IY : Destination operand address register for block data manipulation instruction Base register for variable-length bit field manipulation instruction Destination operand address register for BCD string operation instruction 190 APPENDIX B ADDRESSING MODES B.1 Instruction Address The instruction address is automatically incremented each time an instruction is executed. In addition, the instruction execution sequence can be controlled in various ways, as follows: (1) Direct addressing In this addressing mode, 2- or 4-byte immediate data in the instruction byte is directly loaded to PC or PS or both PC and PS, and is used as a branch address. This addressing mode is used to execute the following instructions: CALL far-proc CALL memptr16 CALL memptr32 BR BR BR far-label memptr16 memptr32 (2) Relative addressing In this addressing mode, 1- or 2-byte immediate data in the instruction byte is added as a signed displacement value to PC and is used as a branch address. If an 8-bit displacement is used, it is sign-extended and is added to PC as 16-bit data. When the displacement is added, the contents of PC indicate the first address of the following instructions, and this addressing mode is used to execute the following instructions. CALL BR BR Conditional branch instruction (3) Register addressing In this addressing mode, the contents of any 16-bit register specified by the 3-bit register specification field in the instruction byte are loaded to PC as a branch address. Unlike when data is used, all the eight 16-bit registers (AW, BW, CW, DW, IX, IY, SP, and BP) can be used. This addressing mode is used to execute the following instructions: Example CALL regptr16 BR regptr16 CALL AW BR BW near-proc near-label short-label short-label 191 APPENDIX B ADDRESSING MODES (4) Register indirect addressing In this addressing mode, the contents (word or double word) of the memory addressed by a 16-bit register (IX, IY, or BW) specified by the register specification field in the instruction byte are loaded to PC (or both PC and PS) as a branch address. Example CALL memptr16 CALL memptr32 BR BR memptr16 memptr32 CALL WORD BR BR WORD PTR [IX] PTR [BW] CALL DWORD PTR [IY] DWORD PTR [IX] Remark The assembler generates the instruction code of memptr16 for the instruction for which WORD PTR is specified, and the instruction code of memptr32 for the instruction for which DWORD PTR is specified. (5) Indexed addressing In this addressing mode, the 1- or 2-byte immediate data in the instruction byte is added as a signed displacement to a 16-bit index register (IX or IY), and the contents (word or double word) addressed by the result of the addition are loaded to PC as a branch address. This addressing mode is used to execute the following instructions. Example CALL memptr16 CALL memptr32 BR BR memptr16 memptr32 CALL var [IX] [2] CALL var [IY] BR BR var [IY] var [IX+4] Remark If variable var has a word attribute, the assembler generates the instruction code of memptr16. If the variable has a double word attribute, the assembler generates the instruction code of memptr32. (6) Based addressing In this addressing mode, the 1- or 2-byte immediate data in the instruction byte are added to a 16-bit base register (BP or BW) as a signed displacement value, and the contents (word or double word) addressed by the result of the addition are loaded to PC as a branch address. This addressing mode is used to execute the following instructions. Example CALL memptr16 CALL memptr32 BR BR memptr16 memptr32 CALL var CALL var BR BR var var [BP+2] [BP] [BW] [2] [BP] Remark If variable var has a word attribute, the assembler generates the instruction code of memptr16. If the variable has a double word attribute, the assembler generates the instruction code of memptr32. 192 APPENDIX B ADDRESSING MODES (7) Based indexed addressing In this addressing mode, the 1- or 2-byte immediate data in the instruction byte as a signed displacement value, the contents of a 16-bit base register (BP or BW), and the contents of a 16-bit index register (IX or IY) are added, and the contents (word or double word) of memory addressed by the result of the addition are loaded to PC as a branch address. This addressing mode is used to execute the following instructions. Example CALL memptr16 CALL memptr32 BR BR memptr16 memptr32 CALL var CALL var BR BR var var [BP] [IX] [BW+2] [IY] [BW] [2] [IX] [BP+4] [IY] Remark If variable var has a word attribute, the assembler generates the instruction code of memptr16. If the variable has a double word attribute, the assembler generates the instruction code of memptr32. B.2 Memory Operand Address The following several modes are used to address registers and memory to be manipulated when an instruction is executed. (1) Register addressing In this mode, the contents of the register specification field (reg = 3-bit field, sreg = 2-bit field) in the instruction byte address the register to be manipulated. reg specifies, in combination with 1 bit (W) that specifies a word or byte in the instruction byte, eight types of word registers (AW, BW, CW, DW, BP, SP, IX, and IY) and eight types of byte registers (AL, AH, BL, BH, CL, CH, DL, and DH). sreg specifies four types of segment registers (PS, SS, DS0, and DS1). In some cases, the operation code of an instruction specifies a specific register. This addressing mode is used to execute the instructions having the following operand description format. Format reg reg16 reg8 sreg acc Example If the case of MOV reg, reg' MOV MOV BP, SP AL, CL Description AW, BW, CW, DW, SP, BP, IX, IY, AL, AH, BL, BH, CL, CH, DL, DH AW, BW, CW, DW, SP, BP, IX, IY AL, AH, BL, BH, CL, CH, DL, DH PS, SS, DS0, DS1 AW, AL 193 APPENDIX B ADDRESSING MODES (2) Immediate addressing In this addressing mode, the 1- or 2-byte immediate data in the instruction byte is manipulated as is. This mode is used to execute the instruction having the following operand description format. Format imm imm16 imm8 pop-value Description 8-/16-bit immediate data 16-bit immediate data 8-bit immediate data 16-bit immediate data In the case of imm, the assembler judges the value of imm described as the operand or the attribute of another operand described at the same time to identify whether the data is 8 or 16 bits long, to determine word/byte specification bit W. Example In the case of MOV reg, imm MOV MUL AL, 5; Byte AW, BW, 1000H In the case of MUL reg16, reg16, imm16 (3) Direct addressing In this mode, the immediate data in the instruction byte addresses the memory to be manipulated. This mode is used to execute the instruction having the following operand description format. Format mem dmem imm4 Example In the case of MOV mem, imm MOV MOV WORD_VAR, 2000H AL, BYTE_VAR In the case of MOV acc, dmem Description 16-bit variable specifying 8- or 16-bit memory data 16-bit variable specifying 8- or 16-bit memory data 4-bit variable indicating bit length of bit field data (4) Register indirect addressing A 16-bit register (IX, IY, or BW) specified by the memory specification field (mod, mem) in the instruction byte addresses the memory to be manipulated. This mode is used to execute the instruction having the following operand description format. Format mem Example In the case of SUB mem, reg SUB [IX], [AW] Description [IX], [IY], [BW] 194 APPENDIX B ADDRESSING MODES (5) Auto-increment/decrement addressing This addressing mode is a type of the register indirect addressing mode. In this mode, the register or memory to be manipulated is addressed by the contents of a default register, and then the contents of the default register are automatically incremented/decremented (+1/1 in the case of byte processing and +2/2 in the case of word processing). By using this addressing mode, the address is automatically updated for the next byte/word operand processing. Whether the register is incremented or decremented is indicated by the direction flag (DIR). If DIR = 0, the register is incremented; if it is 1, the register is decremented. This addressing mode is applicable to all the following default registers and is used to execute the instruction with the following operand description mode. Format dst-block src-block Default register IY IX This addressing mode is used in combination with a counter (CW) that counts the number of times a byte/ word operand is repeatedly processed to control block data processing. (6) Indexed addressing In this addressing mode, 1- or 2-byte immediate data in the instruction byte is added to a 16-bit index register (IX or IY) as a signed displacement value, and the result of this addition is used to address the memory operand to be manipulated. This addressing mode is effective for accessing data of array type. The displacement specifies the start address of the array, and the contents of the index register specifies an array at the nth position from the start address. This addressing mode is used to execute the instruction having the following operand description format. Format mem mem16 mem8 Example In the case of TEST mem, imm TEST TEST TEST BYTE_VAR [IX], 7FH BYTE_VAR [IX+8], 7FH WORD_VAR [IX] [8], 7FFFH Description var [IX], var [IY] var [IX], var [IY] var [IX], var [IY] Remark If variable var has a byte attribute, a byte operand is specified. If var has a word attribute, a word operand is specified. The assembler generates an instruction code corresponding to each operand. 195 APPENDIX B ADDRESSING MODES (7) Based addressing In this addressing mode, 1- or 2-byte immediate data in the instruction byte is added as a signed displacement value to a 16- bit base register (BP or BW), and the result of the addition addresses the memory operand to be manipulated. This addressing mode is effective for accessing data of structure type that is located at several positions in memory. The base register specifies the start address of each structure, and the displacement selects one element in each structure. This addressing mode is used to execute the instruction having the following description format. Format mem mem16 mem8 Example In the case of SHL mem, 1 SHL SHL SHL BYTE_VAR [BP], 1 WORD_VAR [BP+2], 1 BYTE_VAR [BP] [4], 1 Description var [BP], var [BW] var [BP], var [BW] var [BP], var [BW] Remark If variable var has a byte attribute, a byte operand is specified. If var has a word attribute, a word operand is specified. The assembler generates an instruction code corresponding to each operand. (8) Based indexed addressing In this addressing mode, 1- or 2-byte immediate data in the instruction byte as a signed displacement value, the contents of a 16-bit base register (BP or BW), and the contents of a 16-bit index register (IX or IY) are added, and the result of the addition addresses the memory operand to be manipulated. Because one piece of data can be specified by changing the contents of both the base register and index register, this addressing mode is very effective for accessing data of structure type including an array type. The base register specifies the first address of each structure, the displacement value indicates an offset from the first address of the structure to the first address of array data, and the index register indicates the nth position of the array data. This addressing mode is used to execute the instruction having the following operand description format. Format mem mem16 mem8 Example In the case of PUSH mem16 PUSH PUSH PUSH WORD_VAR [BP] [IX] WORD_VAR [BP+2] [IX+6] WORD_VAR [BP] [4] [IX] [8] Description var [base register][index register] var [base register][index register] var [base register][index register] 196 APPENDIX B ADDRESSING MODES (9) Bit addressing In this addressing mode, 3- or 4-bit immediate data in the instruction byte, or the low-order 3 or 4 bits of the CL register specify 1 bit of the 8- or 16-bit register or memory to be manipulated. If an instruction is executed in this addressing mode, a specific 1 bit of a register or memory can be tested (judgment of 0 or 1), set, cleared, or inverted without your having to be aware of the contents of the other bits. This means that byte or word data does not need to be prepared to manipulate only 1 bit, like when the AND or OR instruction is used. This addressing mode is used to execute the instruction having the following description format. Format imm4 imm3 CL Example TEST1 TEST1 NOT1 NOT1 CLR1 CLR1 SET1 SET1 reg8, CL AL, CL reg8, imm3 CL, 5 mem16, CL WORD_VAR [IX], CL mem16, imm4 WORD_VAR [BP], 9 Description Bit number of word operand Bit number of byte operand CL 197 [MEMO] 198 APPENDIX C INSTRUCTION MAP [Legend] Low Order High Order 0H Low-order nibble (Table C-1: low-order 4 bits of first byte, Tables C-3 and C-4: low-order 4 bits of second byte) 0H ADD Mnemonic Condition included in instruction code (Refer to below.) b, f, rm High-order nibble (Table C-1: high-order 4 bits of first byte, Tables C-3 and C-4: high-order 4 bits of second byte) [Condition included in instruction code] b d f i ia id l m rm s sr t v w : Executes byte operation : Uses direct addressing : Involves reading from registers in CPU : Uses immediate data : Uses immediate data and writes data back to accumulator : Uses indirect addressing : Involves control between segments : Uses memory data : Has effective address field in second byte : Uses sign-extended 16-bit immediate data : Uses segment register : Writes registers in CPU : Indirectly specifies port number : Executes word operation reg8 : Uses 8-bit register For the symbols other than above, refer to Table 2-4 Legend of Description on Instruction Format and Operand. 199 APPENDIX C INSTRUCTION MAP Table C-1. Instruction Map (1/2) (a) Native mode Low Order High Order 0H 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH ADD b, f, rm ADD w, f, rm ADDC w, f, rm AND w, f, rm XOR w, f, rm INC CW PUSH CW POP R BNV ADD b, t, rm ADDC b, t, rm AND b, t, rm XOR b, t, rm INC DW PUSH DW ADD w, t, rm ADDC w, t, rm AND w, t, rm XOR w, t, rm INC BW PUSH BW ADD b, ia ADDC b, ia AND b, ia XOR b, ia INC SP PUSH SP ADD w, ia ADDC w, ia AND w, ia XOR w, ia INC BP PUSH BP PUSH DS1 PUSH SS DS1: POP DS1 POP SS ADJ4A OR b, f, rm SUBC b, f, rm SUB b, f, rm OR w, f, rm SUBC w, f, rm SUB w, f, rm CMP w, f, rm DEC CW POP CW MUL w, i BP OR b, t, rm SUBC b, t, rm SUB b, t, rm CMP b, t, rm DEC DW POP DW PUSH s, i BPE OR w, t, rm SUBC w, t, rm SUB w, t, rm CMP w, t, rm DEC BW POP BW MUL s, i BPO OR b, ia SUBC b, ia SUB b, ia CMP b, ia DEC SP POP SP INM b BLT OR w, ia SUBC w, ia SUB w, ia CMP w, ia DEC BP POP BP INM w BGE PUSH PS PUSH DS0 PS: Group3 1H ADDC b, f, rm POP DS0 ADJ4S 2H AND b, f, rm 3H XOR b, f, rm SS: ADJBA CMP b, f, rm DS0: ADJBS 4H INC AW INC IX PUSH IX FPO2 0 INC IY PUSH IY FPO2 1 BH DEC AW POP AW PUSH w, i BN DEC IX POP IX OUTM b BLE DEC IY POP IY OUTM w BGT 5H PUSH AW 6H PUSH R CHKIND Undefined REPNC REPC 7H BV BC BL BNC BNL BE BZ BNE BNZ BNH 8H Imm b, rm Imm w, rm Imm Imm TEST TEST w, rm XCH BP XCH b, rm XCH IX XCH w, rm XCH IY MOV b, f, rm MOV w, f, rm MOV b, t, rm MOV w, t, rm POLL MOV sr, f, rm PUSH PSW LDEA MOV POP b, s, rm w, s, rm b, rm XCH DW MOV XCH BW MOV XCH SP sr, t, rm rm POP PSW LDM LDMB LDMW w MOV BP, i BRK 1 FPO1 FPO1 FPO1 MOV MOV 9H NOPNote XCH CW CVTBW CVTWL CALL l, d TEST STM STMB STMW b, ia MOV AW, i w, ia MOV CW, i b MOV DW, i PSW, AH AH, PSW CMPM CMPM AH MOV MOV MOVBK MOVBK CMPBK CMPBK TEST MOVBKB MOVBKB CMPBKB CMPBKB MOVBKW MOVBKW CMPBKW CMPBKW STM STMB STMW w MOV BW, i RET 1 FPO1 LDM LDMB LDMW b MOV SP, i BRK 3 FPO1 CMPMB CMPMB CMPMW CMPMW b MOV IX, i BRKV w MOV IY, i RETI AL, m BH MOV AL, i CH Shift b, i DH Shift AW, m MOV CL, i Shift w, i Shift m, AL MOV DL, I RET (SP) Shift m, AW MOV BL, I RET b MOV AH, i MOV DS1 w MOV CH, i MOV DS0 b MOV DH, i MOV b, i, rm w MOV BH, i MOV w, i, rm PREPARE DISPOSE RET 1, (SP) FPO1 FPO1 Shift CVTBD CVTDB Undefined TRANS FPO1 TRANSB b EH w b, v w, v BCWZ IN b IN w NOT1 OUT b OUT w 0 CALL d 1 BR d SET1 2 BR l, d DI 3 BR si, d EI 4 IN b, v CLR1 5 IN w, v SET1 6 OUT b, v 7 OUT w, v DBNZE DBNZE DBNZ FH BUSLOCK Undefined REPNE REP REPNZ REPE REPZ HALT Group1 Group1 CLR1 Group2 Group2 CY b w CY CY DIR DIR b w Note Same operation code as XCH AW, AW : The instruction in Groups 1 and 2, and Imm, and Shift are determined by bits 3 through 5 of the second byte of the instruction code (refer to Table C-2). The instruction in Group3 is determined by the second byte of the instruction code (refer to Table C-4). Caution 200 APPENDIX C INSTRUCTION MAP Table C-1. Instruction Map (2/2) (b) Emulation modeNote Low Order High Order 0H 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH NOP LXI B, nn STAX (nn) STAX (nn) SHLD (nn) STA (nn) MOV B, D MOV D, D MOV H, D MOV M, D ADD D SUB D ANA D ORA D JNZ nn JNC nn JPO nn JP nn INX B INX D INX H INX SP MOV B, E MOV D, E MOV H, E MOV M, E ADD E SUB E ANA E ORA E JMP nn OUT n XTHL INR B INR D INR H INR M MOV B, H MOV D, H MOV H, H MOV M, H ADD H SUB H ANA H ORA H CNZ nn CNC nn CPO nn DCR B DCR D DCR H DCR M MOV B, L MOV D, L MOV H, L MOV M, L ADD L SUB L ANA L ORA L PUSH B PUSH D PUSH H PUSH PSW MVI B, n MVI D, n MVI H, n MVI M, m MOV B, M MOV D, M MOV H, M HLT RCL Undefined DAD B LDAX B LDAX D LHLD (nn) LDA (nn) MOV C, D MOV E, D MOV L, D MOV A, D ADC D SBB D XRA D CMP D JZ nn DCX B DCX D DXC H DCX SP MOV C, E MOV E, E MOV L, E MOV A, E ADC E SBB E XRA E CMP E INR C INR E INR L INR A MOV C, H MOV E, H MOV L, H MOV A, H ADC H SBB H XRA H CMP H DCR C DCR E DCR L DCR A MOV C, L MOV E, L MOV L, L MOV A, L ADC L SBB L XRA L CMP L CALL nn MVI C, n MVI E, n MVI L, n MVI A, n MOV C, M MOV E, M MOV L, M MOV A, M ADC M SBB M XRA M CMP M ACI n RRC - 1H Undefined LXI D, nn RAL Undefined DAD D RAR 2H Undefined LXI H, nn DAA Undefined DAD H CMA 3H Undefined LXI SP, nn SCF Undefined DAD SP CMC 4H MOV B, B MOV B, C MOV D, C MOV H, C MOV M, C ADD C SUB C ANA C ORA C POP B MOV B, A MOV D, A MOV H, A MOV M, A MOV C, B MOV E, B MOV L, B MOV A, B ADC B SBB B XRA B CMP B RZ MOV C, C MOV E, C MOV L, C MOV A, C ADC C SBB C XRA C CMP C RET MOV C, A MOV E, A MOV L, A MOV A, A ADC A SBB A XRA A CMP A RST I RST 3 RST 5 RST 7 5H MOV D, B 6H MOV H, B 7H MOV M, B 8H ADD B ADD M SUB M ANA M ORA M ADI n SBI n ANI n ORI n ADD A SUB A ANA A ORA A RST 0 RST 2 RST 4 RST 6 9H SUB B AH ANA B BH ORA B CH RNZ Undefined CZ nn IN n XCHG CC nn CPE nn EI CM nn - DH RNC POP D RC Undefined JC nn Undefined SBI n Group0 XRI n Undefined CPI n - - EH RPO POP H RPE PCHL JPE nn FH RP POP PSW DI CP nn RM SPHL JM nn Caution : The instruction in Group0 is determined by the second byte of the instruction code (refer to Table C-3). Note Subject: other than V33A and V53A 201 APPENDIX C INSTRUCTION MAP Table C-2. Group1, Group2, Imm, and Shift Codes Note Table C-3. Group0 CodesNote Low Order High Order 0H 000 ADD 001 OR 010 ADDC 011 SUB 100 AND 101 SUB 110 XOR 111 CMP 0H DH FH Imm Shift ROL ROR ROLC RORC SHL SHR Undefined SHRA Group1 TEST Undefined NOT rm DEC rm CALL id NEG rm CALL l, id MULU rm BR id MUL rm BR l, id DIVU rm PUSH rm DIV rm Undefined EH CALLN rm Group2 INC rm i FH RETEM Note Bits 5 through 3 of second byte Note Subject: other than V33A and V53A undefined code. Remark The blank column indicates an Table C-4. Group3 Codes Low Order High Order 0H 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 1H TEST1 b TEST1 w CLR1 b SUB4S CLR1 w SET1 b SET1 w NOT1 b CMP4S NOT1 w TEST1 i, b ROL4 TEST1 i, w CLR1 i, b ROR4 CLR1 i, w SET1 i, b SET1 i, w NOT1 i, b NOT1 i, w 2H ADD4S 3H INS EXT INS i EXT i reg8 reg8 EH BRKXANote 1 i FH RETXANote 1 BRKEMNote 2 i i Notes 1. V33A and V53A only (undefined code for other than V33A and V53A) 2. Other than V33A and V53A (Undefined code for V33A and V53A) Remark The blank column indicates an undefined code. 202 APPENDIX D CORRESPONDENCE OF MNEMONICS OF PD8086 AND 8088 The instruction set of the 16-bit V series is upward-compatible with the PD8086 and 8088. Table D-1 shows register correspondence between the PD8086/8088 and 16-bit V series, and Table D-2 shows mnemonic correspondence. Table D-1. Register Correspondence with PD8086 and 8088 PD8086, 8088 AL CL DL BL AH CH DH BH 16-Bit V Series AL CL DL BL AH CH DH BH PD8086, 8088 AX CX DX BX SP BP SI DI 16-Bit V Series AW CW DW BW SP BP IX IY 203 APPENDIX D CORRESPONDENCE OF MNEMONICS OF PD8086 AND 8088 Table D-2. Mnemonic Correspondence with PD8086 and 8088 PD8086, 8088 16-Bit V Series PD8086, 8088 16-Bit V Series PD8086, 8088 16-Bit V Series PD8086, 8088 16-Bit V Series AAA AAD AAM AAS ADC ADD AND CALL CBW CLC CLD CLI CMC CMP CMPS ADJBA CVTDB CVTBD ADJBS ADDC ADD AND CALL CVTBW CLR1 CY CLR1 DIR DI NOT1 CY CMP CMPBK/ CMPBKB/ CMPBKW CS: CWD DAA DAS DEC DIV DS: ES: ESC HLT IDIV IMUL IN INC INT INT 3 INTO IRET JA JAE PS: CVTWL ADJ4A ADJ4S DEC DIVU DS0: DS1: FPO1 HALT DIV MUL IN INC BRK BRK 3 BRKV RETI BH BNC/BNL JB JBE JC JCXZ JE JG JGE JL JLE JMP JNA JNAE JNB JNBE JNC JNE JNG JNGE JNL JNLE JNO JNP JNS JNZ JO JP JPE JPO JS JZ LAHF LDS LEA LES LOCK LODS BC/BL BNH BC/BL BCWZ BE/BZ BGT BGE BLT BLE BR BNH BC/BL BNC/BNL BH BNC/BNL BNE/BNZ BLE BLT BGE BGT BNV BPO BP BNE/BNZ BV BPE BPE BPO BN BE/BZ MOV AH, PSW MOV DS0 LDEA MOV DS1, BUSLOCK LDM/LDMB/ LDMW SHL LOOP LOOPE LOOPNE LOOPNZ LOOPZ MOV MOVS MOVSB MOVSW MUL NEG NOP NOT OR OUT POP POPF PUSH PUSHF RCL RCR REP REPE REPNE REPNZ REPZ RET ROL ROR SAHF SAL SAR SBB SCAS DBNZ DBNZE DBNZNE DBNZNE DBNZE MOV MOVBK MOVBKB MOVBKW MULU NEG NOP NOT OR OUT POP POP PSW PUSH PUSH PSW ROLC RORC REP REPE REPNE REPNZ REPZ RET ROL ROR MOV PSW, AH SHL SHRA SUBC CMPM/ CMPMB/ CMPMW SHL SUB TEST WAIT XCHG XLAT XLATB XOR SHR SS: STC STD STI STOS SHR SS: SET1 CY SET1 DIR EI STM/STMB/ STMW SUB TEST POLL XCH TRANS TRANSB XOR ADD4S BRKEM BEKXA CALLN CHKIND CMP4S DISPOSE EXT FPO2 INM INS OUTM PREPARE REPC REPNC RETEM RETXA ROL4 ROR4 SUB4S TEST1 Remark : No corresponding instruction 204 APPENDIX E INSTRUCTION INDEX (mnemonic: by function) [Data transfer] LDEA ... 94 MOV ... 97 TRANS ... 165 TRANSB ... 165 XCH ... 166 [Addition/subtraction] ADD ... 13 ADDC ... 17 SUB ... 155 SUBC ... 159 [BCD operation] [Repeat prefix] REP ... 124 REPC ... 126 REPE ... 124 REPNC ... 127 REPNE ... 128 REPNZ ... 128 REPZ ... 124 [Primitive block transfer] CMPBK ... 61 CMPBKB ... 61 CMPBKW ... 61 CMPM ... 63 CMPMB ... 63 CMPMW ... 63 LDM ... 95 LDMB ... 95 LDMW ... 95 MOVBK ... 100 MOVBKB ... 100 MOVBKW ... 100 STM ... 153 STMB ... 153 STMW ... 153 [Bit field manipulation] EXT ... 81 INS ... 92 [Input/output] IN ... 88 OUT ... 114 [Primitive input/output] INM ... 90 OUTM ... 115 ADD4S ... 15 CMP4S ... 59 ROL4 ... 136 ROR4 ... 141 SUB4S ... 157 [Increment/decrement] DEC ... 72 INC ... 89 [Multiplication/division] DIV ... 75 DIVU ... 77 MUL ... 102 MULU ... 105 [BCD adjustment] ADJ4A ... 19 ADJ4S ... 20 ADJBA ... 21 ADJBS ... 22 [Data conversion] CVTBD ... 65 CVTBW ... 66 CVTDB ... 67 CVTWL ... 68 [Compare] CMP ... 57 [Complement operation] NEG ... 107 NOT ... 109 205 APPENDIX E INSTRUCTION INDEX (mnemonic: by function) [Logical operation] AND ... 23 OR ... 112 TEST ... 161 XOR ... 167 [Bit manipulation] CLR1 ... 54 NOT1 ... 110 SET1 ... 144 TEST1 ... 163 [Shift] SHL ... 147 SHR ... 149 SHRA ... 151 [Rotate] ROL ... 134 ROLC ... 137 ROR ... 139 RORC ... 142 [Subroutine control] CALL ... 49 RET ... 129 [Stack manipulation] DISPOSE ... 74 POP ... 118 PREPARE ... 120 PUSH ... 122 [Branch] BR ... 41 [Conditional branch] BC ... 25 BCWZ ... 26 BE ... 27 BGE ... 28 BGT ... 29 BH ... 30 BL ... 25 BLE ... 31 BLT ... 32 BN ... 33 BNC ... 34 BNE ... 35 BNH ... 36 BNL ... 34 BNV ... 37 BNZ ... 35 BP ... 38 BPE ... 39 BPO ... 40 BV ... 48 BZ ... 27 DBNZ ... 69 DBNZE ... 70 DBNZNE ... 71 [Interrupt] BRK ... 43 BRKV ... 45 CHKIND ... 52 RETI ... 132 [CPU control] BUSLOCK ... 47 DI ... 73 EI ... 80 FPO1 ... 83 FPO2 ... 85 HALT ... 87 NOP ... 109 POLL ... 117 [Segment override prefix] DS0: ... 79 DS1: ... 79 PS: ... 79 SS: ... 79 [Emulation mode control] BRKEM ... 44 CALLN ... 51 RETEM ... 131 [Extended address mode control] BRKXA ... 46 RETXA ... 133 206 APPENDIX F INSTRUCTION INDEX (mnemonic: alphabetical order) [A] ADD ... 13 ADD4S ... 15 ADDC ... 17 ADJ4A ... 19 ADJ4S ... 20 ADJBA ... 21 ADJBS ... 22 AND ... 23 [B] BC ... 25 BCWZ ... 26 BE ... 27 BGE ... 28 BGT ... 29 BH ... 30 BL ... 25 BLE ... 31 BLT ... 32 BN ... 33 BNC ... 34 BNE ... 35 BNH ... 36 BNL ... 34 BNV ... 37 BNZ ... 35 BP ... 38 BPE ... 39 BPO ... 40 BR ... 41 BRK ... 43 BRKEM ... 44 BRKV ... 45 BRKXA ... 46 BUSLOCK ... 47 BV ... 48 BZ ... 27 [C] CALL ... 49 CALLN ... 51 CHKIND ... 52 CLR1 ... 54 CMP ... 57 CMP4S ... 59 CMPBK ... 61 CMPBKB ... 61 CMPBKW ... 61 CMPM ... 63 CMPMB ... 63 CMPMW ... 63 CVTBD ... 65 CVTBW ... 66 CVTDB ... 67 CVTWL ... 68 [D] DBNZ ... 69 DBNZE ... 70 DBNZNE ... 71 DEC ... 72 DI ... 73 DISPOSE ... 74 DIV ... 75 DIVU ... 77 DS0: ... 79 DS1: ... 79 [E] EI ... 80 EXT ... 81 [F] FPO1 ... 83 FPO2 ... 85 [H] HALT ... 87 [I] IN ... 88 INC ... 89 INM ... 90 INS ... 92 [L] LDEA ... 94 207 APPENDIX F INSTRUCTION INDEX (mnemonic: alphabetical order) LDM ... 95 LDMB ... 95 LDMW ... 95 [M] MOV ... 97 MOVBK ... 100 MOVBKB ... 100 MOVBKW ... 100 MUL ... 102 MULU ... 105 [N] NEG ... 107 NOP ... 108 NOT ... 109 NOT1 ... 110 [O] OR ... 112 OUT ... 114 OUTM ... 115 [P] POLL ... 117 POP ... 118 PREPARE ... 120 PS: ... 79 PUSH ... 122 [R] REP ... 124 REPC ... 126 REPE ... 124 REPNC ... 127 REPNE ... 128 REPNZ ... 128 REPZ ... 124 RET ... 129 RETEM ... 131 RETI ... 132 RETXA ... 133 ROL ... 134 ROL4 ... 136 ROLC ... 137 ROR ... 139 ROR4 ... 141 RORC ... 142 [S] SET1 ... 144 SHL ... 147 SHR ... 149 SHRA ... 151 SS: ... 79 STM ... 153 STMB ... 153 STMW ... 153 SUB ... 155 SUB4S ... 157 SUBC ... 159 [T] TEST ... 161 TEST1 ... 163 TRANS ... 165 TRANSB ... 165 [X] XCH ... 166 XOR ... 167 208 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-889-1689 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Corporation Semiconductor Solution Engineering Division Technical Information Support Dept. Fax: 044-548-7900 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 96.8 Excellent Good Acceptable Poor ...
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This note was uploaded on 06/02/2010 for the course CS 1 taught by Professor Nec during the Spring '10 term at Tsinghua University.

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