HW5 - DB = X’A XB Z = XB For this circuit(a Draw the...

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EE 2301 S 2010 INTRODUCTION TO DIGITAL SYSTEMS DESIGN HOMEWORK # 5 (15 pts) Due Mar 23, 2010 1. Complete the timing diagram below for a JK FF that triggers off the trailing edge of the clock and has active low Clear and Preset inputs. 2. Design a master-slave D flip-flop using only NAND gates. Note: you can also use inverters because an inverter can be implemented using 2- input NAND gate via (X X)’ 3. A sequential circuit with two D flip-flops A and B, two inputs X and Y, and one output Z, is specified by the following input equations: DA = X’A + XY
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Unformatted text preview: DB = X’A + XB Z = XB For this circuit: (a) Draw the logic diagram, (b) Derive the state table, (c) Draw the state diagram. 4. Problem 13.2 5. Problem 13.7 6. For the synchronous circuit implementing single-input, single-output sequential machine, described by the following state table, derive an output sequence for the input sequence X=0110001 assuming that the starting state is:: (a) B (b) C next state output Present State x=0 x=1 x=0 x=1 --------------------------------------------------- A B C 1 1 B D D 1 0 C B C 0 1 D C A 0 1...
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This note was uploaded on 06/04/2010 for the course EE 2301 taught by Professor Larrykinney during the Spring '09 term at Minnesota.

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HW5 - DB = X’A XB Z = XB For this circuit(a Draw the...

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