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EE 2301 S 2010 INTRODUCTION TO DIGITAL SYSTEMS DESIGN HOMEWORK #8 (20 pts) Due May 6, 2010 1. Derive the input equations for JK flip-flop implementation of the control network for a serial adder, shown on p. 5 of lecture notes Set 9. 2. (a) Draw a block diagram for a parallel multiplier that can multiply two binary numbers where the multiplier is 3 bits and the multiplicand is 4 bits. Use an 8-bit shift register along with other necessary blocks. (b) Draw a state diagram for the multiplier control (c) Illustrate the operation of the multiplier when 11 is multiplied by 5. Specify the sequence of add and shift pulses generated by the control network and specify the contents of the 8-bit register at each clock time. 3. Construct an SM block that has 3 inputs(A, B, C ), 4 outputs (W,X,Y,Z) and two exit paths. For this block, output Z is always 1, and W is 1 iff A and B are both 1. If C=1 and A=0, Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and exit path 2 is taken. 4.
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