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Unformatted text preview: 1 EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe Lecture 7. PN Junction under Bias • PN junctions in reverse bias – Carrier concentrations – Charge storage and the smallsignal depletion capacitance • PN junctions in forward bias – Minority carrier boundary conditions: the law of the junction – Carrier transport: qualitative understanding – Quasineutrality: established after dielectric relaxation EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe A built in potential, V bi , provides a barrier to majority carrier current. If an external bias is applied to the junction with the N side +ve, P side ve, the barrier to majority carrier Fow is increased. P N E φ φ p n f E i φ i φ i e – holes PN Junction in Thermal Equilibrium V bi V bi 2 EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe Applied voltage appears essentially entirely across the depletion region. The total potential drop across the junction is , V biV A . p N – – – – + + + + – – – – + + + + V A Ohmic contact V A dropped here Negligible voltage dropped here + Biased PN Junction + + V A EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe Reverse Biased Junction ( V A < 0) V A e – holes e – holes – + Drift Drift Diffusion Diffusion E fn E fp 3 EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe E ¡ feld across depletion region increases. W increases, mobile carriers pulled Further away From junction. Minority carrier current ¡ow is no longer zero, but it is very small (leakage) ¢or step junctions, From Eq. (10) and (11): (14) i.e., V bi is replaced by ( V bi V A ) (Note V A is negative) ( ) 2 / 1 1 1 2 Υ Φ Τ Σ Ρ − Ο Ο Π Ξ Μ Μ Ν Λ + = + = A bi D A o s n p V V N N q K x x W ε ( ) W V V A bi − = 2 (15) Reverse Biased Junction ( V A < 0) E MAX 4 EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe The small signal capacitance of the junction is given by (16) where A = crosssectional area This result holds for any arbitrary doping proFle. Given any proFle, if W is determined, the small signal capacitance C can be calculated. W depends on the dopant proFle and the applied bias W AK dV dQ C o s A ε = = PN Junction Capacitance EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe Qualitative ChargeVoltage Plot Compare with Q = C V 5 EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe Charge, Field and Potential for Reverse Bias V D < 0 V EE 216 Principles and Models of Semiconductor Devices (Winter 2010) K. C. Saraswat and R. T. Howe Charge Storage in pn Junction • Circuit element: 6...
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This note was uploaded on 06/05/2010 for the course EE 216 taught by Professor Harris,j during the Fall '09 term at Stanford.
 Fall '09
 Harris,J

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