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**Unformatted text preview: **Classification of Digital Circuits ¡ Combinational. ¢ Output depends only on current input values. ¡ Sequential. ¢ Output depends on current input values and present state of the circuit, where the present state of the circuit is the current value of the devices memory. ¢ Also called finite state machines. State of a Circuit ¡ The contents of storage elements. ¡ A collection of know internal signal values that contain information about the past necessary to account the future behavior of the circuit. Bi-stable Element (Simple Memory) ¡ The simplest sequential circuit. ¡ It consist of a pair of inverters connected as shown below. Notice the feedback loop. A B Digital Analysis ¡ Two stable states. ¡ If A is HIGH then the lower inverter has a HIGH at its input and a LOW at its output. This in turn forces the upper inverters input to be LOW and its output to be HIGH. ¡ If A is LOW then the lower inverter has a LOW at its input and a HIGH at its output. This in turn forces the upper inverters input to be HIGH and its output to be LOW. Analog Analysis ¡ Considering the steady state behavior of the bistable element. ¢ V in1 = V out2 ¢ V in1 = T(V in2 ) ¢ V in1 = T(V out1 ) ¢ V in1 = T(T(V in1 )) V out1 = V out2 V in1 = V in2 stable metastable stable Transfer function: V out1 = T ( V in1 ) V out2 = T ( V in2 ) V in1 V out1 V out2 V in2 Q Q_L Analog Analysis ¡ Metastable behavior: ¢ Consider the middle intersecting point in the diagram shown below. ¢ What would happen if a small amount of noise varies either input voltage. V out1 = V out2 V in1 = V in2 stable metastable stable Analog Analysis ¡ The drawing on this slide shows a very good analogy to the stable and metastable behavior of a bi- stable element. stable stable metastable Clock ¡ Signal that determines the change of state in most sequential circuits. CLK t per t H t L t L t H t per state changes occur here (a) state changes occur here CLK_L (b) duty cycle = t H / t per frequency = 1 / t per period = t per duty cycle = t L / t per Latches and Flip-Flops ¡ Binary cells capable of storing 1 bit of information. ¡ Generates one of two possible stable states. ¡ Two outputs labeled Q and Q. ¡ One or more inputs. Latches and Flip-Flops ¡ These sequential devices differ in the way their outputs are changed: ¢ The output of a latch changes independent of a clocking signal. ¢ The output of a flipflop changes at specific times determined by a clocking signal. Basic Latch Memory element Alarm Sensor Reset Set On Off Reset Set Q S-R Latch S R Q a Q b 1 1 1 1 0/1 1/0 1 1 (a) Circuit (b) Truth table Time 1 1 1 1 R S Q a Q b Q a Q b ? ? (c) Timing diagram R S t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 (no change) S-R Latch R S Q 1 1 1 1 S R 1 last Q Q 1 ( a) (b) QN last QN QN ¡ SR latch based on NOR gates....

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