lec8 - Review - Single Cycle CPU 0 M u x Add Add 4...

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Reinman 9-2 PC Instruction memory Read address Instruction [31–0] Instruction [20 16] Instruction [25 21] Add Instruction [5 0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch RegDst ALUSrc Instruction [31 26] 4 16 32 Instruction [15 0] 0 0 M u x 0 1 Control Add ALU result M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M u x 1 ALU result Zero PCSrc Data memory Write data Read data M u x 1 Instruction [15 11] ALU control Shift left 2 ALU Address Review -- Single Cycle CPU
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Reinman 9-3 Shift left 2 PC M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] M u x 0 1 M u x 0 1 4 Instruction [15–0] Sign extend 32 16 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5–0] Instruction [31-26] Instruction [5–0] M u x 0 2 Jump address [31-0] Instruction [25–0] 26 28 Shift left 2 PC [31-28] 1 1 M u x 0 3 2 M u x 0 1 ALUOut Memory MemData Write data Address Review -- Multiple Cycle CPU
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Reinman 9-4 Review -- Instruction Latencies Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load Single-Cycle CPU Multiple Cycle CPU Ifetch Reg/Dec Exec Wr Add
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Reinman 9-5 Pipelining Analogy • Pipelined laundry: overlapping execution – Parallelism improves performance • Four loads: – Speedup = 8/3.5 = 2.3 • Non-stop: – Speedup = 2n/(0.5n + 1.5) 4 = number of stages
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Reinman 9-6 IF: Instruction fetch ID: Instruction decode and register fetch EX: Execution and effective address calculation MEM: Memory access WB: Write back A Pipelined Datapath Note: These stages are often labeled with the primary structure in the stage, rather than the main function of the stage: • IF stage = “IM” (instruction memory) • ID stage = “Reg” (register read) • EX stage = “ALU” • MEM stage = “DM” (data memory) • WB stage = “Reg”
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Instruction memory Address 4 32 0 Add Add result Shift left 2 Instruction M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data Address Data memory 1 ALU result M u x ALU Zero IF: Instruction fetch ID: Instruction decode/ register file read EX: Execute/ address calculation MEM: Memory access WB: Write back Warning – “write register” line is incorrect in this figure! Pipelined Datapath
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Reinman 9-8 Execution in a Pipelined Datapath CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 lw lw lw lw lw steady state steady state IF ID EX MEM WB IM Reg ALU DM Reg IF ID EX MEM WB IM Reg DM Reg IF ID EX MEM WB IM Reg DM Reg IF ID EX MEM WB IM Reg DM Reg IF ID EX MEM WB IM Reg DM Reg
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This note was uploaded on 06/09/2010 for the course CS 152 taught by Professor Staff during the Spring '98 term at UCLA.

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lec8 - Review - Single Cycle CPU 0 M u x Add Add 4...

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