lec11

lec11 - The five components Computer Control Input Memory...

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Reinman 11-2 The five components Computer Memory Datapath Control Output Input
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Reinman 11-3 The Problem with Memory • It’s expensive (and perhaps impossible) to build a large, fast memory – “fast” meaning “low latency” • why is low latency important? • To access data quickly: – it must be physically close – there can’t be too many layers of logic • Solution: Move data you are about to access to a nearby, smaller, memory cache – Assuming you can make good guesses about what you will access soon.
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Reinman 11-4 A Memory Hierarchy CPU SRAM memory SRAM memory DRAM memory Disk memory on-chip “level 1” cache off-chip “level 2” cache main memory disk small, fast big, slower, cheaper/bit huge, very slow, very cheap
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Reinman 11-5 Cache Basics • In running program, main memory is data’s “home location”. – Addresses refer to location in main memory. – “Virtual memory” allows disk to extend DRAM • We’ll study virtual memory later • When data is accessed, it is automatically moved into cache – Processor (or smaller cache) uses cache’s copy – Data in main memory may (temporarily) get out-of-date • But hardware must keep everything consistent. – Unlike registers, cache is not part of ISA • Different models can have totally different cache design
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Reinman 11-6 The Principle of Locality • Memory hierarchies take advantage of memory locality. – The principle that future memory accesses are near past accesses. • Two types of locality: – Temporal locality - near in time: we will often access the same data again very soon – Spatial locality - near in space/distance: our next access is often very close to recent accesses. • This sequence of addresses has both types of locality 1, 2, 3, 1, 2, 3, 8, 8, 47, 9, 10, 8, 8 . ..
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Reinman 11-7 What is Cached? • Taking advantage of temporal locality: – bring data into cache whenever its referenced – kick out something that hasn’t been used recently • Taking advantage of spatial locality: – bring in a block of contiguous data (cacheline), not just the requested data. • Some processors have instructions that let software influence cache: – Prefetch instruction (“bring location x into cache”) – “Never cache x” or “keep x in cache” instructions
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Reinman 11-8 Cache Vocabulary • cache hit: access where data is found in the cache • cache miss: access where data is NOT in the cache • cache block size or cache line size: the amount of data that gets transferred on a cache miss. • instruction cache (I-cache): cache that only holds instructions • data cache (D-cache): cache that only holds data • unified cache: cache that holds both data & instructions A typical processor today has separate “Level 1” I- and D-caches on the same chip as the processor (and possibly a larger, unified “L2” on-chip cache.
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Reinman 11-9 Cache Issues • On a memory access – How does hardware know if it is a hit or miss?
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This note was uploaded on 06/09/2010 for the course CS 152 taught by Professor Staff during the Spring '98 term at UCLA.

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lec11 - The five components Computer Control Input Memory...

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