Test2review - . 2. Familiarity with Verilog logic design ....

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Review for Test 2 Midterm Test 2 – 5-7 pm, Monday, 20 October, 641 Dow One-Hour Test—Come any time, preferably by 6 pm Optional Review Session—7:30-9:00, Friday, 17 October, 229 EERC Test Rules Closed Book, closed notes One 8 ½” x 11” summary sheet (both sides) allowed No calculators Course Learning Objectives Covered 1. Combinational logic design including familiarity with Boolean algebraic equations and mastery of Karnaugh maps
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Unformatted text preview: . 2. Familiarity with Verilog logic design . . Wakerly Material Covered Chapter 4 Combinational Logic Design Principles Section 5.4 -- Verilog Possible Problems Karnaugh maps 4- or 5-variable SOP or POS Regular or with dont cares Hazards Verilog design of simple SOP or POS circuits Any problems like assigned homework problems Test Format 4-6 Problems, some with multiple parts 1 2...
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This note was uploaded on 06/16/2010 for the course EE ee2173 taught by Professor Sloan during the Spring '07 term at Michigan Technological University.

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Test2review - . 2. Familiarity with Verilog logic design ....

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