{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Test2review - 2 Familiarity with Verilog logic design...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Review for Test 2 Midterm Test 2 – 5-7 pm, Monday, 20 October, 641 Dow One-Hour Test—Come any time, preferably by 6 pm Optional Review Session—7:30-9:00, Friday, 17 October, 229 EERC Test Rules Closed Book, closed notes One 8 ½” x 11” summary sheet (both sides) allowed No calculators Course Learning Objectives Covered 1. Combinational logic design including familiarity with Boolean algebraic equations and mastery of Karnaugh maps
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: . 2. Familiarity with Verilog logic design . . Wakerly Material Covered Chapter 4 – Combinational Logic Design Principles Section 5.4 -- Verilog Possible Problems Karnaugh maps 4- or 5-variable SOP or POS Regular or with don’t cares Hazards Verilog design of simple SOP or POS circuits Any problems like assigned homework problems Test Format 4-6 Problems, some with multiple parts 1 2...
View Full Document

{[ snackBarMessage ]}