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Unformatted text preview: Section 5.4 Verilog Chapter 6 Combinational Logic Design Practices Chapter 7 Sequential Logic Design Principles (sections 7.1-7.3, 7.4.1, 7.5 only) Possible Problems Decoders Encoders, code converters, including priority encoders Multiplexers 1 Exclusive Or circuits Comparators Adders/Subtracters Cross-coupled NANDs or NORs D, T, SR and JK flipflops Identification of Verilog description of any of the above Analysis of clocked sequential circuit (Finite State Machine) State diagram design Any problems like assigned homework problems Test Format 4-6 Problems, some with multiple parts 2 3...
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- Spring '07