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Test3review - Section 5.4 – Verilog Chapter 6 –...

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Review for Test 3 Midterm Test 3 – 5-7 pm, Monday, 20 November, 135 Fisher **Note Room Change One-Hour Test—Come any time, preferably by 6 pm Optional Review Session—7:30-9:00, Friday, 7 November, 229 EERC Test Rules Closed Book, closed notes One 8 ½” x 11” summary sheet (both sides) allowed No calculators Course Learning Objectives Covered 1. Introduction to SR, JK and T flipflops, familiarity with D flipflops. 2. Familiarity with synchronous sequential logic design using D flipflops, including finite state machines. 3. Introduction to multiplexers, decoders, encoders and code converters. 4. Familiarity with Verilog logic design . . Wakerly Material Covered
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Unformatted text preview: Section 5.4 – Verilog Chapter 6 – Combinational Logic Design Practices Chapter 7 – Sequential Logic Design Principles (sections 7.1-7.3, 7.4.1, 7.5 only) Possible Problems Decoders Encoders, code converters, including priority encoders Multiplexers 1 Exclusive Or circuits Comparators Adders/Subtracters Cross-coupled NANDs or NORs D, T, SR and JK flipflops Identification of Verilog description of any of the above Analysis of clocked sequential circuit (Finite State Machine) State diagram design Any problems like assigned homework problems Test Format 4-6 Problems, some with multiple parts 2 3...
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Test3review - Section 5.4 – Verilog Chapter 6 –...

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