215D_HW2

# 215D_HW2 - EE 215D Sp 07 B Razavi HO#5 Homework#2 Due Mon 1...

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EE 215D B. Razavi Sp. 07 HO #5 Homework #2 Due Mon., April 23, 2007 1. Consider the following sampling circuit, where 600 and 0 4 pF. The circuit has been designed for a 10-bit system. (a) Suppose 0 0and is a constant, 1 . How long does it take the output to reach within 0.5 LSB of ? (b) Suppose 1 sin 2 , 1 0 5V , 35 MHz, and 2 (Nyquist sampling). For the case shown below, how long does it take the output to settle within 0.5 LSB of its “ﬁnal” value? t in V CK Acq. Hold V S 1 C R on H V CK 2. Consider the switched-capacitor SHA shown below, where 1pFand is constant and equal to 1 V. Assume all switches are ideal and model the op amp as shown. S 1 X S S H 3 C L V V V V G V X X V X > +0.2 V < +0.2 V -0.2 V < < -0.2 V Op Amp Model V X (a) At 0 1 and 2 turn off and 3 turns on and 0 0. Plot the output voltage as a function of time and calculate the hold settling time to 0.5 LSB for 14-bit resolution.

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## This note was uploaded on 06/18/2010 for the course CE 01 taught by Professor Bazgei during the Spring '09 term at UCSC.

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215D_HW2 - EE 215D Sp 07 B Razavi HO#5 Homework#2 Due Mon 1...

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