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Unformatted text preview: be (in LSB)? How much error can we tolerate in the gain of the subtractor or the fullscale voltage of the second stage if DNL is to remain below 0.2 LSB? How much comparator offset is allowed in the second stage? 2. Design an 8bit folding and interpolating ADC. Consider two cases: (a) The analog input can be loaded by at most 16 differential pairs. (b) The analog input can be loaded by at most 32 differential pairs. (Assume the input stage of each comparator requires a differential pair.) Provide a diagram similar to that of the 6bit example in the lecture notes for each case, but also show the interpolation network in detail. Summarize the hardware requirements in two tables, showing the total number of differential pairs, comparators, and resistors for each case. (You need not count the load resistors used in the differential pairs.)...
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This note was uploaded on 06/18/2010 for the course CE 01 taught by Professor Bazgei during the Spring '09 term at UCSC.
 Spring '09
 Bazgei

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