215D_HW4 - be (in LSB)? How much error can we tolerate in...

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EE 215D B. Razavi Spring 07 HO #13 Homework #4 Due Mon. May 14, 2005 1. In this problem, we study the effect of nonidealities on the performance of a two-step 10-bit ADC (with 5 bits resolved in each stage). For each of the following errors, explain how the input/output characteristic of the ADC is affected and demonstrate using proper plots (e.g. residue plots, input/output plots, etc.). (a) Comparator in the first stage has an offset voltage of 1 3LSB . (b) The reference ladder of the first stage has an INL of 0 7 LSB at its midpoint. (c) The DAC has an offset voltage of 0 8LSB . (d) The DAC has a gain error of 0 04%. (e) The DAC has a DNL of 1 3LSB . (f) The DAC has an INL of 1 4LSB . (g) The subtractor has an offset of 1 7LSB . (h) The subtractor has a gain error 0
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Unformatted text preview: be (in LSB)? How much error can we tolerate in the gain of the subtractor or the full-scale voltage of the second stage if DNL is to remain below 0.2 LSB? How much comparator offset is allowed in the second stage? 2. Design an 8-bit folding and interpolating ADC. Consider two cases: (a) The analog input can be loaded by at most 16 differential pairs. (b) The analog input can be loaded by at most 32 differential pairs. (Assume the input stage of each comparator requires a differential pair.) Provide a diagram similar to that of the 6-bit example in the lecture notes for each case, but also show the interpolation network in detail. Summarize the hardware requirements in two tables, showing the total number of differential pairs, comparators, and resistors for each case. (You need not count the load resistors used in the differential pairs.)...
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This note was uploaded on 06/18/2010 for the course CE 01 taught by Professor Bazgei during the Spring '09 term at UCSC.

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