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215D_Midterm_Samples

# 215D_Midterm_Samples - EE 215D Midterm Exam Spring 2003...

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Unformatted text preview: EE 215D Midterm Exam Spring 2003 Solution 5 CID.UOO....0.CIIOCCOIDOOOOOIIOIOOIOIIOOODICOOI - Time Limit: 2 Hours Open Book, Open Notes M 13 5 7 91113151719 1. TWO unitymgain samplers appear in a pipeline as shown below. When the ﬁrst stage is in the acquisition mode, the second is in the hold mode and vice versa. Suppose Vin =: l V and model the op amp as shown below. With the initial condition shown in the second stage, detennine the time it takes V0.“ to reach within 0.1% of its ﬁnal value. You can assume the second op amp creates a good virtual ground at its inverting inputin this mode. Sk tch the ' waveform for Vow as the ﬁrst stage goes from sampling to hold. Assume 01 = C; = l pF. é C1 |v,,,l < 0.25 v vin > 0.25 v v.“ < .o.25-v “‘3‘.” Vout "T" Vout “‘7‘ Vout Vin _ any... new Vin _ 1 mA Vin _ 1 mA ‘ -l- .. .. é- - ~1- .. Gm =0.02 U c v Rout =50kQ - ‘ 4 Hold Mode : I + anmam, VL" ext ~1V. at Van = ~Qv 96— -> 5km) mode VG,“ , W” l . MA ‘ "LC: / Vin-3 Vow} -' ' 10km Vrn :-0.2.s M Cd» MD r?o?n+ VOLL“ \$0 meow/id selﬁsh '5)”: W UM. V111- w Van ' @Vw} QM?“ Vow (a): 0.313% *— ‘G'M {U0uk“i): W 4-- C4, dvo‘ﬂ Eon?“ Cit :‘féw~_}.)vow 4. gm 3 42 alt/ms r119 izou‘f 2 so k’ C1~ WF 6; C dVou+ Q + ._L U G _..._. \‘ 9. dt + ( m and) ouJ- -— -+- mi C) \Bu+ (0) = 035 \$0in Esm m OWL” It. (5 +.L " VOLUME) :: m: + *Gm-L + O~?S) e 2 G Gm+ Ruf m+au§r g V (00 3 G“ 2—. 0.05% v. 0u+ ) Gm+__l_~ Roar t » ~__.7' «f. —L memr : 04% Vow—(w) = 0.835 «W. 7: 0 29—3 EC m 0 t I) O- 2153 ‘nsec W'Hmt 71‘ mm Vow:— +0 rear}: 041 can-s Rm“!va J. t;'\‘ ta cs ‘05 b 0.235% —-—‘ 2. A resistor-ladder DAC incorporates MOS switches as resistors in a secondary ladder. The diagram below shows how the secondary ladder slides up and down along the primary one. Is this DAC monotonic for any value of the MOS on—resistance, Ron? Why or why not? Use detailed analysis to support your claim. @ 95—; ‘j are the, same Point bout in MO olIFl. s.mal\ons e, WM “V (fl/(n RD“) , V3: ___,_3_:‘_______......_ \l x V‘“) Y + T/KYlROn) (“Apr (- "” “Pen ’ *0 be. mono-lﬁnlc ___. \IX 3 V3 (:3le +1” //Qn73m 5. 3r ‘3 T// (niacn) 4 4’ (,0ch l5 Wags W714. E13” omj wall/M at? Ron. w W40 DAC is unwocliﬁonalg mmlbnlc Wang WM 03 En. u 3. Consider the two nominallyequal copacitots shown below. The initial condition at node X is zero. (a) Assuming each capacitor can be expressed as C‘ = 00(1 + a] V), determine the value of VX after the transitions shown in the ﬁgure occur. (b) Repeat part (a) ifC = 00(1 + a1V + asz). @ Ct a cl lo (00 5 .x H a ,‘V0 Vo C‘ e. V ’- ~V° - ﬁtﬁ|fﬁ C— COCI+WIV)_ qt ‘4; from com SWt/wh’an oj 0140495 --J Ci. = ‘12 ’ V0‘Vx Vx~(-vo) j C! .0“); : f cadul O O 3. CO (CUO”VX)+O_§ 5: Co ( (VX+V")Y‘ :g" CVc'T'l/ff’) 2(O(\Vo+i) Vx :: o ---o \szo H (b) it: C: Co (/+ oath-CK; vi) Simﬂmij 3 2 co [gurus-i- ? cvo~va+ ﬁg.- cVo-vx>3]=co[<v,c+vc)+°§ when? (va3 2 z :. Vx( \+°(tV9+"(2\/o + 0% Vx)-‘3° 2. .. 2 co Vx : O of Vx 3 3?;- (ihoﬁ VD—g— q/ZUO) 4. Consider a lO-bit two-step ADC similar to that in Homework #4. Each stage resolves 5 bits and the subtractor has a voltage gain of unity. The reference voltage for the ﬁrststage ladder is nominally equal to 1024 LSB and that v for the second~stage ladderequal to 32 LSB. (a) Suppose the reference voltage for the ﬁrst-stage ladder is accidentally chosen to be 2048 LSB but that for the ' second stage is still equal to 32 LSB. Plot the residue and the overall input-output characteristic and determine critical errors. Ass Dune. MC” owfocf Var/25 bdwem o anoé /0 L74 4523,» (b) Suppose the reference voltage for the second-stage ladder is accidentally chosen to be 64 LSB but that for the ﬁrst stage is still equal to 1024 LSB. Plot the residue and the overall input-output characteristic and determine critical errors. @ (a) 1? Wu: reference voltage 0;? f3 3309;: 53 20148 LSB vesfm, 936%,. r; '32 Lee ...
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215D_Midterm_Samples - EE 215D Midterm Exam Spring 2003...

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