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Unformatted text preview: c A.H.Dixon CMPT 150: Week 6 (Feb 11  15, 2008) 38 16 DEMULTIPLEXERS Whereas the multiplexer selects an input port whose value is to be delivered to the output port, the “demultiplexer” selects which output port to deliver the value on its single data input port. The demultiplexer is defined by the following behavioraly description: m1 = d*s1*s0 m2 s1 s0 d m0 m1 m3 m0 = d*s1*s0 m3 = d*s1*s0 m2 = d*s1*s0 The control inputs s1 and s0 determine the output port where the input will be delivered. When d is set “permanently” to the value “1” then the device is more commonly as a “2 × 4 Decoder”. In particular, note that the Boolean functions that define each output correspond to all possible minterms that can be defined with literals s1 and s0 . For this reason the decoder is sometimes called a “minterm generator”. LIke the multiplexer, the demultiplexer is a type of digital switch. However, when configured as a decoder, it can be used to represent any sum of minterms representation where the number of variables of the function matches the number of select inputs of the decoder. That is, for a function of n variables, an n × 2 n decoder is required. For example, to implement the function f ( x,y ) = Σ m (0 , 1 , 3) a 2 × 4 decoder is used, along with an OR gate (see next page). The decoder is used to define all the minterms, then those minterms that are required for the given function are simply “ORed” together. c A.H.Dixon CMPT 150: Week 6 (Feb 11  15, 2008) 39 y m2 s1 s0 d m0 m1 m3 1 x More importantly, a set of functions of n variables can be implement using just one n × 2 n decoder. All that is required is an OR gate to combine the minterms of each function. For example, consider the design of a circuit to add three 1bit values. Its behavioral description is given by: c0 x s y c1 x y c1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 s c0 From the sum of minterms representations, a logic diagram can be obtained im mediately, using a 3 × 8 decoder, since there are three inputs: c 1 = Σ m (3 , 5 , 6 , 7) s = Σ m (1 , 2 , 4 , 7) c1 s2 s1 d 1 x y c0 s0 m7 m6 m5 m4 m3 m2 m1 m0 s c A.H.Dixon CMPT 150: Week 6 (Feb 11  15, 2008) 40 17 UNSIGNED ADDITION The circuit to add three 1bit values obtained in the previous section is commonly called a “1bit full adder” (“FA” for short). This component is a basic building block of most arithmetic circuits, including larger adders. The behavioral description for a 4bit full adder is: (c4,s3,s2,s1,s0) = (x3,x2,x1,x0) plus (y3,y2,y1,y0) plus c0 xo y0 c0 c4 s0 y3 y2 y1 x3 x2 x1 s3 s2 s1 FA Observe that it is the sum of two 4bit values x 3 x 2 x 1 x and y 3 y 2 y 1 y and one 1bit value c 0. Since the sum of two 4bit value can produce a result that requires five bits to represent it, there are five output bits; s is the least significant bit and c 4 is the most significant bit of the sum....
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 Spring '08
 Dr.AnthonyDixon
 Addition, Binary numeral system, Negative and nonnegative numbers, significant bit

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