{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

SFU - CMPT 150 - Lectures - Week 7

SFU - CMPT 150 - Lectures - Week 7 - c A.H.Dixon CMPT 150...

Info icon This preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
c A.H.Dixon CMPT 150: Week 7 (Feb 18 - 22, 2008) 54 The simple storage cell given on the top of the next page is used to construct the circuit immediately underneath it. The accompanying waveform diagram illustrates the “dynamic” behavior of this circuit for a given series of input assignments to the data input x . The control input in connected to a clock generator, to provide regular periods when the individual components are enabled. The output w will only be observed to change when c changes from 1 to 0. That is, any change to the output can only occur on the transition of c from 1 to 0, and no changes will be observed when c is held constant at 0 or 1. The contents of a sequential system at any given time is called its state . If a sequential circuit is enabled by a control input c , then c is called a trigger for the sequential system. A sequential system is level-triggered if it can change its state while the trigger is held constant at logic-0 or logic-1. A sequential system is edge-triggered if it can only change state on the transition of the trigger. If the change can occur when the transition is from logic-0 to logic-1 it is called “ postive edg-triggered ” and if the change can occur only on the transtion from logic-1 to logic-0 it is said to be negative edged-triggered .” As a consequence, simple devices can be provided in one of four ways: 1. logic-0 level-triggered, 2. logic-1 level-triggered, 3. positive edge-triggered, 4. negative edge-treggered. One-bit level-triggered memory elements are called “latches”, while their edge- triggered equivalents are called “flip-flops”.
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
c A.H.Dixon CMPT 150: Week 7 (Feb 18 - 22, 2008) 55 w X C Q C 0 1 Q+ <- X Q+ <- Q function X X Q Q C C x c w function c Q2+ <- Q1 Q1+ <- x Q2+ <- Q2 Q1+ <- Q1 0 1 c Q1 Q2 x 1 2
Image of page 2
c A.H.Dixon CMPT 150: Week 7 (Feb 18 - 22, 2008) 56 19 SEQUENTIAL CIRCUIT DESIGN While it is possible to design sequential circuits using only gates and feedback loops, the “memory” components of a sequential circuit are normally provided using pre-defined latches or flip-flops. Such components are typical building-blocks in the same way as gates. Just as the behavioral description of a gate or other combinational component must be known in order to use them to design a circuit, so the behavioral descriptions of flip-flops and latches is required to incorporate them into a design.
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern