This preview shows pages 1–4. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: c A.H.Dixon CMPT 150: Week 8 (Feb 25  29, 2008) 64 22 COUNTERS A modn counter is a register that generates the same sequence of n values repeatedly. The most common examples are incrementing mod2 n counters as these counters repeat the sequence: , 1 , 2 ,..., 2 n 1 that is, the remainders upon dividing any integer by 2 n . However, the sequence may be strictly increasing, strictly decreasing, or may just be an particular sequence of integers, The following are all examples o sequences generated by mod4 counters: , 1 , 2 , 3 , , 1 , 2 , 3 , ,... 3 , 2 , 1 , , 3 , 2 , 1 , , 3 ,... 1 , 2 , 3 , 4 , 1 , 2 , 3 , 4 , 1 ,... 2 , 4 , 6 , 8 , 2 , 4 , 6 , 8 , 2 ,... 4 , 1 , 6 , 2 , 4 , 1 , 6 , 2 , 4 ,... Depending on the sequence, a variety of techniques are available to design sequen tial circuits that will generate any sequence: 1. Flipflop implementation from the characteristic table. 2. Bitslice design. 3. Register (MSI) level design. The first two methods have been demonstrated previously. In particular, a mod4 incrementing counter was constructed from its characteristic table, and assignment 3 employed bitslice design to develop a mod4 counter and a mod8 counter. The following examples will illustrate register level design. Register level design uses MSI components rather than gates as the basic building blocks of the circuit. MSI is short for medium scale integration and refers to components such as multiplexers, demultiplexers, adders, and registers. As an example, consider the design of an incrementing mod16 counter with par allel load. The behavior of such as device is given by: From the function select table, it is apparent that this is a multifunction device. Therefore a solution can be obtained by designing a solution for each row of the table. Since there are only two meaningful rows in the table, there are two so lutions. One requires a circuit to add 1 to the current contents of the register, c A.H.Dixon CMPT 150: Week 8 (Feb 25  29, 2008) 65 x3 ld up 3 2 3 2 R 1 1 ld up function 1 1 1 1 R+ < R (no change) R+ < R plus 1 R+ < (x3, x2, x1, x0) (not used) x0 x1 x2 while the second solution requires that an external input be supplied to the reg ister. The choice of which result to deliver to the register is made with four 2x1 MUXes. c0 c4 1 2 3 1 2 3 3 2 1 1d0 1d1 2d0 d21 3d0 3d1 4d0 4d1 s ld 4m 3m 2m 1m MUX2 x4 FA R 3 2 1 3 2 1 1 up ld x3 x2 x1 x0 controller Q0 Q1 Q2 Q3 The design also includes components to map the external control inputs ld and up to the internal control inputs of the circuit ( s and lr . This mapping is described by the following function table: ld up s lr X 1 1 1 1 1 1 1 X X c A.H.Dixon CMPT 150: Week 8 (Feb 25  29, 2008) 66 The entity defined by this function table is called a controller . Every time it is necessary to map external inputs to the control inputs of the components, a controller subcircuit is required....
View Full
Document
 Spring '08
 Dr.AnthonyDixon

Click to edit the document details