SFU - CMPT 150 - Lectures - Week 9

SFU - CMPT 150 - Lectures - Week 9 - c A.H.Dixon CMPT 150:...

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Unformatted text preview: c A.H.Dixon CMPT 150: Week 9 (Mar 3 - 7, 2008) 74 28 DATA TRANSFER BETWEEN REGISTERS The interconnection of register components is a common occurrence in more com- plex digital systems. Therefore it is important to understand how the trigger of a clock transition in a synchronous circuit affects the transfer of data from one component to another. Consider the following logic diagram: x(3...0) R1 R2 ld ld ld1 ld2 4 4 4 Now suppose that both control inputs ( ld1 and ld2 ) are set to 1. The effect of a single clock transition that enables the two registers simultaneously is to transfer data from one register to the next without the value being loaded into the first register leaking through the the second and being loaded there as well. This cannot happen on a single transition because the amount of time when the registers are enabled is equal to the transition time from logic-0 to logic -1 and this time is much less that the propagation delay of either register. In particular, if the output of register R2 is connected to the input of register R1, then on a single clock transition it is possible to swap the values in the two registers without the need for a third register to temporarily hold the contents of one of the registers being swapped. 28.1 Bus Sharing It is common to see several buses connected to or sharing a common bus. How- ever, for such a connection to be viable, bus conflicts must be resolved. A bus conflict occurs when two or more signal lines or buses attempt to define the value on a signal line or bus to which both are connected. Not only is the logic of such a connection ambiguous, but it can damage the components. Therefore to facilitate such connections, a component called a tri-state buffer is used. This device is like a digital switch that when not enabled, effectively c A.H.Dixon CMPT 150: Week 9 (Mar 3 - 7, 2008) 75 disconnects an input signal from its output port. The behavioral description of a tri-state buffer is given in the following diagram: 4 1 1 1 1 y x en Z Z 1 "Z" denotes "high impedance" (i.e., disconnected) y en x TS 4-bit bus buffer 4 When several such devices are packaged so that they share a common enable, the device is called a bus buffer and provides a means of connect output buses from individual components to a single bus,so that access to the bus by the component can be controlled. The entity diagram for a bus buffer (labeled TS) is shown in the previous diagram....
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This note was uploaded on 06/20/2010 for the course CMPT 150 taught by Professor Dr.anthonydixon during the Spring '08 term at Simon Fraser.

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SFU - CMPT 150 - Lectures - Week 9 - c A.H.Dixon CMPT 150:...

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