mcelwee_MS_thesis - An Automated Analog Layout Generation...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: An Automated Analog Layout Generation Flow by Patrick T. McElwee Research Project Submitted to the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, in partial satisfaction of the requirements for the degree of Master of Science, Plan II . Approval for the Report and Comprehensive Examination: Committee: Professor Robert W. Brodersen Research Advisor (Date) * * * * * * * Professor Jan M. Rabaey Second Reader (Date) An Automated Analog Layout Generation Flow Patrick McElwee i 5/21/2004 TABLE OF CONTENTS CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CHAPTER 2 BASICS OF ANALOG LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 MOSFET Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Resistor Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Capacitor Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Analog Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CHAPTER 3 EXISTING LAYOUT GENERATION TOOLS . . . . . . . . . . . . . . . . . . . 22 CHAPTER 4 AUTOMATED ANALOG LAYOUT GENERATION . . . . . . . . . . . . . 24 4.1 Components of the Layout Generation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Using the Layout Generation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.1 Determining the Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.2 Creating the Necessary Schematic Blocks . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.2.1 Creating the Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.2.2 Placing the Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.2.3 Creating Pins and Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2.3 Starting the Layout Generation Program . . . . . . . . . . . . . . . . . . . . . . . . . 41 CHAPTER 5 DEVICE FILE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CHAPTER 6 DESIGN EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 Device File Driven OTA Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.2 Schematic Driven OTA Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 CHAPTER 7 CONCLUSIONS AND FUTURE WORK . . . . . . . . . . . . . . . . . . . . . . . . 64 APPENDICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Appendix A Source Code Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Appendix B Code Description...
View Full Document

This note was uploaded on 06/29/2010 for the course EE 33 taught by Professor Smith during the Spring '10 term at École Normale Supérieure.

Page1 / 91

mcelwee_MS_thesis - An Automated Analog Layout Generation...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online