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Unformatted text preview: DeviceLevel Placement for Analog Layout:
An Opportunity for NonSlicing Topological Representations FIOrin Balas’a
University of Illinois at Chicago, Dept. of EECS, Chicago, IL 60607 Abstract— Layout design for analog circuits has
historically been a time consuming, errorprone, man
ual task. Its complexity results not so much from
the number of devices, as from the complex interac
tions among devices or with the operating environ
ment, and also from continuousValued performance
speciﬁcations. This paper addresses the problem of devicelevel
placement for analog layout in a nontraditional way.
Different from the traditional approaches — explor
ing a huge search space with a combinatorial opti
mization technique, where the cells are represented
by means of absolute coordinates, being allowed to
illegally overlap during their moves in the chip plane
— this paper advocates the use of nonslicing topo
logical representations, like (symmetric—feasible) se
quence—pairs, ordered— and binary trees. Exten
sive tests, processing industrial analog designs, have
shown that using skillfully the symmetry constraints
(very typical to analog circuits) to remodel the solu
tion space of the encoding systems, the topological
representation techniques can achieve a better com
putation speed than the traditional approach, while
obtaining a similar high quality of the designs. 1 Introduction In recent years, complete systems that before occupied sep
arate chips are being integrated on a single chip. Examples
of such systems on a chip (SoC’s) include telecommunica—
tions IC’s, wireless designs — as components in RF receivers
and transmitters, and networking interfaces. Although most
functions in such integrated systems are implemented with
digital circuitry, the analog circuits needed at the interface
between the electronic system and the real world are now
being integrated on the same die for reasons of cost and
performance. 281 Layout design for analog circuits has historically been
a time consuming, errorprone, manual task. If layout for
digital 10’s is usually regarded as a difﬁcult task mainly
because of the scale of the problem (but also complex de
lay modeling, timing optimization), analog circuits and the
analog portions of mixedsignal systemson—chip are signiﬁ
cantly smaller — usually up to 100 devices in a cell, and less
than 20,000 devices in a complete subsystem [11]. The task
complexity for analog layout results not so much from the
sheer number of devices, as from the complex interactions
among devices or with the operating environment, and also
continuous—valued performance speciﬁcations. As most ana
log circuits are very distinct among themselves, today they
are usually still designed and laid out by hand. This paper addresses an essential problem of analog lay—
out design — the device—level analog placement — in a non
traditional way, using recent results on topological repre
sentations for nonslicing ﬂoorplans. The traditional way of
approaching the analog placement problem is to explore a
huge search space with a combinatorial optimization method
(for instance, simulated annealing) where the cells are rep
resented by means of absolute coordinates and they can ille—
gally overlap during their moves in the chip plane. However,
the topological representations — the main focus of the re
search plan — are based on a different idea: to deﬁne an
encoding system as a solution space, each code representing
a feasible placement conﬁguration. While the classic absolute representation approach trades
of? a larger number of (annealing) moves for easier and
quicker—to—build layout conﬁgurations which may not be al
ways physically realizable, the idea of using topological rep
resentations is to trade off more complex (but physically cor
rect!) layout constructions for a smaller number of moves.
Our research results show that the skillful use of symme—
try constraints (very typical to analog circuits) can remodel
the encoding systems, diminishing signiﬁcantly the solution
space size and, therefore, making its exploration more effec
tive in comparison with the classic approaches. The paper is organized as follows: Section 2 discusses the
slicing and nonslicing topological representations of place—
ment conﬁgurations; then, Section 3 presents the device
level analog placement problem and discusses several tech 0—78036633—6/01/510.00 ©2001 IEEE. niques to solve it based on different topological representa—
tions; ﬁnally, Section 4 gives an overview of the experimental results, and Section 5 presents the basic conclusions of this
research. 2 Topologicalrepresentations The topological representations of ﬂoorplans got recently a
renewed attention in the context of block placement. A brief historical overview will introduce many concepts used along
this paper. The block placement problem subject to nonoverlapping
constraints, often called packing, was proven to be NPhard
even for rectangular blocks [8]. The nature of the problem
entailed the use of combinatorial optimization methods (as
simulated annealing, genetic algorithms) to explore the so
lution space of placement conﬁgurations. A combinatorial optimization method can equally op
erate with two classes of representations of block conﬁgu
rations. The most straightforward and widely used is the
absolute (or flat) representation, where the positions of the
blocks are directly speciﬁed in terms of coordinates relative
to an arbitrary system of axes in the chip plane [2]. How
ever, the convergence of the exploration may be slow clue to
the huge size of the search space (which contains also infea
sible placement conﬁgurations, since blocks are allowed to
illegally overlap). An alternative approach to the absolute representation is
to deﬁne a set of codes — each code representing a placement
conﬁguration — as a solution space. An encoding system of
feasible placement conﬁgurations is usually referred to as a topological representation, being an encryption of the posi
tioning (topological) relations between any pair of modules. The ﬁrst tOpological representation was derived from the
slicing ﬂoorplan model where the blocks are organized in
a set of slices which recursively bisect the layout horizon—
tally and vertically. The direction and nesting of the slices
is recorded in a (binary) slicing tree or, equivalently, in a
normalized Polish expression (see, tag, [2]). The slicing representation limits the set of layout topolo
gies. This can degrade layout density, especially when cells
are very different in size, which is often the case in ana
log layout. Consequently, it was widely acknowledged that
slicing placement is not a good choice for highperformance
analog design. This is the reason why topological represen
tations were in general disregarded, and the most effective
analog placement tools existent so far employed simulated
annealing — as optimization engine — operating with absolute
placement representations [2, 6, 7]. More recently, several novel topological representations,
not restricted to slicing floorplan topologies, have been pro 282 pOsed. Murata et al. suggested to encode the ”leftright”
and ”updown” positioning relations between cells using two sequences of cell permutations, named sequence pair [8]. Nakatake et al. devised a metagrid structure (called boundedsliceline
grid) without physical dimensions to define orthogonal rela—
tions between modules [9]. Guo ct al. proposed the Otree
data structure to reduce the drawback effect of redundancies
in the two previous representations [3]. The advent of nonslicing topological representations is
likely to have an important impact in devicelevel placement
for analog layout, as the superiority claim 7 undisputed until
recently — of the absolute representation for analog layout
becomes questionable. Although Kahng expressed some concerns regarding topo
logical representations in general — as scalability, or ”the
packing obsession” [4], these concerns are hardly justiﬁed in
our context. Scalability to instances of hundreds of thou—
sands of cells is a problem indeed, but only for digital cir—
cuits. Our results are very effective (see Section 4), even
when processing reallife analog placement problems, where
part of the blocks are ”sof ” capacitors or having a num
ber of alternative realizations. Moreover, the optimization
deals with a complex cost function with multiple objectives
subject to "hard” and ”sof ” constraints. The problem of analog placement is a perfect opportu
nity for nonslicing topological representations to prove their practical value.
3 Devicelevel analog placement In order to automatically produce analog devicelevel lay
outs matching in density and performance the highquality
manual layouts, an analog placement tool must be provided
with the capability of dealing with analogspeciﬁc features: 1) The ability to deal with topological constraints for
symmetry and device matching. In highperformance analog circuits it is often required
that groups of devices are placed symmetrically with respect
to one or several axes. Analog circuits use very often dif
ferential architectures based on electrically symmetric net
works, and therefore, layout symmetry matches the induced
parasitics in the two halves of a group of devices. Symme
try is also used to prevent unwanted oscillations by balanc
ing thermal couplings in differential structures, or to reduce
the thermal sensitivity of the circuit. In order to reduce
systematically—induced mismatches — produced by dissimi
lar geometrical choices, matching groups of devices should
be constrained to the same orientation and variant. 2) The ability to arrange devices such that critical struc—
tures are shared in common (device merging or geometry sharing) in order to reduce both layout density and induced
parasitics. 3) The existence of a library of device generators and
the ability to exploit their reshaping capability. The devicematching constraints and the geometry shar—
ing situations can be handled relatively easy when using
topological encodings 1) by imposing constraints at the
move—set level of the combinatorial optimization algorithm
employed to explore the set of topological representations,
2) by introducing penalty terms in the cost function, and
3) by modifying the procedure which builds the placement
conﬁgurations from the topological encodings. However, dealing efﬁciently with symmetry constraints
in the framework of topological representations has proven
to be a problem of unexpected difﬁculty. In our ﬁrst empiri—
cal tests using the sequencepair representation [8], we were
initially tempted to perform minor changes to the search
space exploration: if the current encoding proved to be con—
sistent with the symmetry constraints then the cost of the
placement conﬁguration would be evaluated and the an—
nealing algorithm would operate normally; otherwise, the
current encoding would be infeasible (in symmetry point of
View) and, therefore, disregarded. Unfortunately, such a
simple solution proved to be extremely ineffective, the com—
putation times being disappointingly high (see Section 4).
The main reason was revealed to be the huge number of
encodings infeasible with respect to symmetry constraints,
which was overwhelming versus the ”symmetricfeasible”
ones [1]. This experiment led to the following conclusion: a topo
logical representation proves to be effective only if the analog
placement tool is able to explore only those encodings which
comply with the imposed set of symmetry constraints. This
obviously better strategy encounters two hurdles though: aL) given symmetry constraints, without building the correspond how to recognize the encodings complying with the ing layout ? b) how to efﬁciently restrict the exploration (performed
by a combinatorial optimization, like simulated annealing)
only to the subspace of these ”symmetric—feasible” (SF) en
codings ? 3.1 Using S—F sequencepairs In the case of the sequence—pair representation [8], the ques tions above have already received satisfactory answers [1]. Let (a, 6) be the sequencepair of a placement conﬁgura
tion containing a number of symmetry groups (each group
composed of pairs of symmetric blocks, and selfsymmetric
blocks relative to a common vertical axis). Denoting by a:
the position of block A in sequence o (as a can be viewed as a onetoone mapping, (1—1 is welldeﬁned) and deﬁning sim
ilarly of, and also denoting by sym(zc) the block symmetric to 2:, the sequencepair (01,)6) is called symmetricfeasible 283 Figure 1:
pairs (a) (CDAFBGE, DCBGAFE) ; (b) (EBAFCDG,
EBCDFAG) Block placement encoded by the sequence— (SF) if for any distinct blocks z, y in any of the symmetry
groups ——1 1
as —1
sym(:r) — #1
(S) < a9 <2 Bsymw) < Fig. 1 displays two placement conﬁgurations correspond
ing to the sequencepairs (CDAFBGE, DCBGAFE) and
(EBAFCDG, EBCDFAG'), respectively. Assuming the
existence of a symmetry group composed of the pairs of sym
metric cells (C', D) and (B, G), and the selfsymmetric cells
A and F, the ﬁrst encoding is infeasible and the correspond
ing placement does not verify the symmetry constraints; the
second sequence—pair is symmetricfeasible — in the sense of
condition (S), leading to a correct placement solution. The exploration of the sequencepair encodings using
simulated annealing can be restricted to the symmetric—
feasible codes as follows: it is sufﬁcient to start the search
from an initial sequence—pair which can be easily built to ver—
ify condition (S) (for instance, corresponding to a placement
where the symmetric pairs in any symmetry group top one
another) and, afterwards, to constrain the move—set of the
optimizer such that the property (S) of symmetricfeasibility
is preserved: for instance, if two cells from symmetric pairs
are interchanged in sequence a, then their symmetric coun
terparts must be also interchanged in sequence ,6, etc. According to our tests (see Section 4), the strategy de
scribed above has proven highly beneﬁcial in terms of both
computation time and quality of solutions. The basic reason
is that, instead of exploring a search space of size (n!)2 — the
total number of sequence—pairs for n placeable cells (over 25
million for the illustrative example in Fig. 1), only a reduced
part this space (having the size1 (nl)2/(2p + s)! , where p
is the number of symmetric pairs and s is the number of
selfsymmetric cells) is explored, i.e. the sequence—pairs ver—
ifying condition (S) — which are only 35,280 for this simple
example. 3.2 Using Otrees The use of the Otree representation [3] (see F ig. 2a) has
also produced good results employing the algorithm pro—
posed by Pang et al. [10] due mainly to the fact that the 1A more general formula is proven in [1]. (a) (b) Figure 2: (a) Otree representation, (b) binary tree repre—
sentation of the block placement in Fig. 1a number of Otrees (therefore, the search space) is always
smaller than the number of sequence—pairs, the former rep—
resentation exhibiting less redundancy than the latter. For
the example in Fig. 1 (n [5] 71411 ( 2: >  77.! than the total number of sequence—pairs (over 25 million), 7), the number of O—trees is 2,162,160 — signiﬁcantly smaller but still larger than the total number of symmetricfeasible
sequence—pairs2 (i.e., 35,280 when p = s = 2). The exploration of the O—trees is done with simulated
annealing as well. After each new Otree is generated, a ver—
iﬁcation routine  having the complexity 0(n2) — attempts
to detect as early as possible whether the current encoding is
symmetricfeasible or not. Two constraint graphs — vertical
GU and horizontal Gh — are built taking into account both
the positioning constraints derived from the Otree and from
the given symmetry constraints. The Otre‘e is symmetric
feasible if G}. is acyclic and GU does not contain positive
cycles [10]. Only in this case the move is considered for
acceptance, according to the probabilistic hill—climbing of
the annealer. Otherwise, the move is immediately rejected as the placement built from the Otree cannot satisfy the
symmetry Constraints. 3.3 Using SF binary trees Binary trees can lead to a better performance than both the
sequencepair and the O—tree representations: while offering
in general the same solution space size as the Otrees (due
to a one—toone mapping property [5]), in the presence of
symmetry constraints the exploration can be restricted to a
proper subset of binary trees ~ which were called symmetric
feasible (SF) binary trees. Let ((leftSubtree)root rightSubtree) and
(root(leftSubtree) rightSubtree) be the recursive inorder
and, respectively, preorder representations of a binary tree.
Let (7, 6) be the pair of sequences3 derived from the inorder 2However, when the asymmetric part of the circuit is larger, the
number of Otrees can become smaller than the number of symmetric—
feasible sequencepairs (e.g., if in Fig. 1 there is only one symmetric
pair of Cells: 1) : 1 and s = 0). 9Usually (7,5) is not equal to the sequencepair representation
(a,[3). There are sequences a and B which do not correspond to the
inorder and preorder traversals of any binary tree: such a sequence 284 and preorder representations by dropping the parentheses
(used only to express the tree structure). Using the same
notations as for sequence—pairs, the binary tree encoding is
called Symmetric feasible (S—F) relative to a symmetry group
G' if for any distinct blocks m, y in G: (5') —1
’71 1 —1 symw) —1
syn—1.0:) 4:6 <5 <7; The SF binary trees have a desirable property: their
number is smaller than both the SF sequencepairs and 0
trees. Indeed, if all the blocks in the layout are organized
in a symmetry group (n 2 2p), the number of (labeled) S—F 1 2P ) .pmr 5 (2p)! which is the binary trees is [5] m 1) number of symmetricfeasible sequencepairs when n : 2p .
The annealing algorithm can be adapted to explore only the subspace of S—F binary trees rather than the whole space of binary trees: (1) the initial binary tree must be symmetric feasible. If (ahbi) are 17 pairs of symmetric blocks, such a
binary tree is, e.g., (a1 » . ‘ap bp    b1 . . ), using the preorder
traversal representation; (2) the moves during the explo
ration (changes of the binary tree codes) are chosen such that property (8’) continues to hold. 3.4 Using the absolute representation A complementary placement tool using the absolute repre
sentation (brieﬂy presented in Section 2) has been imple
mented as well. The tool employs virtual symmetry axes
(7], having mobile positions, to model multiple symmetry
groups. 4 Experimental results A placement tool for analog layout has been implemented
and embedded in a retargetable object symbolic environ»
ment for layout design. The tool can use alternative opti
mization algorithms based both on the absolute representa
tion (similar to other traditional approaches), and on differ
ent topological representations. In order to ensure a correct
comparative evaluation, the simulated annealing schedule is
identical for all the placement algorithms. The results pre—
sented below have been obtained on an HP 9000/ 777 work
station. ‘ Fig. 3 displays two placement solutions — one obtained
using SF sequence—pairs, the other using SF binary trees
a of a 110cell analog circuit having six symmetry groups.
Fig. 4 shows other two examples, the ﬁrst obtained using the
absolute representation, the second 7 based on O—trees. Note
that in all these examples, the (usually large) capacitors are
soft cells, which shapes are optimized and regenerated at
the end of the placement. pair is, for instance, (CAB, ABC). Table 1 displays the results obtained for several analog
blocks, components of a digital spread spectrum transceiver
used in cordless telephone applications and wireless modems.
The conclusions derived from thes...
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