6B_2 - Design Automation for Analog: The Next Generation of...

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Design Automation for Analog: The Next Generation of Tool Challenges Rob A. Rutenbar Dept. of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA, USA rutenbar@ece.cmu.edu ABSTRACT The decade of the 1990s saw the first wave of practical “post- SPICE” tools for analog designs. A range of synthesis, optimization, layout and modeling techniques made their way from academic prototypes to first-generation commercial offerings. We offer some pragmatic prognostications for what the next wave might (or, more bluntly, should ) focus on next, as pressure to improve AMS design productivity grows. Categories and Subject Descriptors B.7.2 [ Integrated Circuits ]: Design Aids General Terms Analog, Algorithms, Design, Synthesis. Keywords Analog, mixed-signal, integrated circuits, computer-aided design 1. INTRODUCTION Over the last roughly half dozen years, analog design automation tools “got real” in one important sense: a range of synthesis, optimization, modeling and layout tools moved from concept demonstrations (most commonly academic) to first-generation, supported commercial offerings. We refer to these as “post- SPICE” tools; this is convenient shorthand for one unifying characteristic of these tools – the characteristic of interest in this paper – the fact that they were not simulation tools. To be sure, simulators saw significant advances as well in this time frame. But for the first time, we also saw some tools specifically aimed at synthesis and optimization emerge, for sizing, for centering, for layout, and so forth. Several recent publications survey this current terrain nicely [1-3]. Based on our own experiences, with the CMU analog toolset [4-6] and its industrial progeny [7-9] we offer the following as the essential components of the current state of the art: Simulation-based sizing synthesis: these tools support circuit-level sizing, biasing, and centering. They employ global numerical optimization techniques for robustness, and network-of-workstations parallelism for speed. The key idea is full SPICE-level simulation for each solution candidate proposed during optimization. The strategy has two key virtues: it can be used for any design (i.e., any fixed topology) that one can simulate; and it produces designs that pass designer-provided simulation scripts. These tools optimally reuse the verification infrastructure that all circuit designers already build for each circuit they create. And it produces “trustworthy” results, since one can immediately see that they simulate correctly, using the designer’s own simulator. Optimization-based layout: these tools replicate at device level what ASIC-level floorplanning, placement, and routing tools do at chip level. The key components are a library of generators for common device-level analog structures (e.g., analog PCELLS), and device-level placement and shape-level routing tools sensitive to analog issues such as symmetries, crosstalk and parasitic balance. There are several examples of successes at the analog cell level
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This note was uploaded on 06/29/2010 for the course EE 33 taught by Professor Smith during the Spring '10 term at École Normale Supérieure.

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6B_2 - Design Automation for Analog: The Next Generation of...

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