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09_par_caps

# 09_par_caps - EECE 416/501 Analog Circuit Design Parasitic...

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EECE 416/501 Analog Circuit Design Parasitic Capacitors and Layout Considerations Christopher M. Twigg Assistant Professor Department of Electrical and Computer Engineering B INGHAMTON U N I V E R S I T Y S T A T E U N I V E R S I T Y O F N E W Y O R K November 15, 2009

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Parasitic Caps : Open-Loop Bode Response, Phase Margin Open-Loop Response + - V id + - C 1 C 2 V o A v1 = G M1 ∙R out1 A v2 = G M2 ∙R out2 X = G M1 C 1 · G M2 C 2 τ 1 = R out1 · C 1 τ 2 = R out2 · C 2 V o (s) V id (s) = X (s+ 1 / τ 1 ) · (s+ 1 / τ 2 ) = X s 2 +( 1 / τ 1 + 1 / τ 2 ) · s+ 1 / ( τ 1 · τ 2 ) 10 0 10 1 10 2 10 3 10 4 10 5 -40 -20 0 20 40 Magnitude (dB) 10 0 10 1 10 2 10 3 10 4 10 5 -150 -100 -50 0 Phase (deg) Frequency (Hz) EECE 416/501, C. M. Twigg November 15, 2009 2/13
Parasitic Caps : Closed-Loop Bode Response Closed-Loop Response + - V i C 1 C 2 V o A v1 = G M1 ∙R out1 A v2 = G M2 ∙R out2 X = G M1 C 1 · G M2 C 2 τ 1 = R out1 · C 1 τ 2 = R out2 · C 2 V o (s) V i (s) = X s 2 +( 1 / τ 1 + 1 / τ 2 ) · s+ 1 / ( τ 1 · τ 2 ) +X 10 0 10 1 10 2 10 3 10 4 10 5 -50 -40 -30 -20 -10 0 Magnitude (dB) PM = 25 deg PM = 45 deg PM = 65 deg 10 0 10 1 10 2 10 3 10 4 10 5 -150 -100 -50 0 Phase (deg)

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