p2 - EECE 416/501 Fall 2009 Project 2 Introduction to the...

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EECE 416/501 Project 2 Due 10/08/2008 Fall 2009 Introduction to the Cadence Design Tools, Part II This project is to be completed individually. Academic Honesty Policy All students must adhere to the Student Academic Honesty Code of the University and the Watson School. The Electrical and Computer Engineering Department has adopted a standard policy to enforce these codes for course work violations. Category I violations result in a grade of 0 for the graded work plus a full letter grade reduction for the course. A Report of Category I Academic Dishonesty form is filed with the Provost's Office; if a prior report is already on file, the offense is automatically elevated to Category II. Category II violations result in at least a failing grade for the course plus any additional penalties determined by the Watson Academic Integrity Committee. Goal and General Description The purpose of this project is to introduce you to the Cadence Virtuoso custom integrated circuit tools. As part of this introduction, you will be generating the physical layout for the high-gain amplifier circuit of Project 1. MATLAB will also be introduced as a way to analyze and plot collected data. Procedure Transient Simulation Open your simulation file from project 1 and change the value of the capacitor from 1 pF to 1 aF . This will minimize the effect of the capacitor, which is only there to eliminate the warning that would have resulted if we left the amplifier output floating. Change the DC source driving your input to a pulse source, vpulse . You may need to delete the DC source and instantiate the pulse source. Set Voltage 2 to 5 V , the delay to 1 ns , the rise and fall times to 100 ps , the pulse width to 10 us , and the period to 20 us . Now start the ADE and load/set the variables as you did before. Choose the “a” and “y” nets to be plotted. Instead of a DC simulation, we are now going to perform a transient simulation. From the ADE menu, select Analyses => Choose… 9/28/2009 1/10
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EECE 416/501 Project 2 Due 10/08/2008 Fall 2009 Introduction to the Cadence Design Tools, Part II Under the “tran” analysis, enter a Stop Time of 2 ns , as illustrated to the left. Click on the Enabled button, and then press OK . Run the simulation to produce a plot similar to the one to the right. Save the generated data using the ocnPrint command and the VT(<net>) function. You can now close the simulation and ADE window. You’ll probably want to save the state. Layout With Cadence running and your library selected, create a new schematic by selecting File => New => Cell View… in the library manager. Fill in the Cell Name (this should be the same name you used last time to create a schematic and symbol) and make sure layout appears under the View Name box and the tool is Virtuoso . Press OK to create the new cell and open the blank layout.
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This note was uploaded on 06/30/2010 for the course EECE 501 taught by Professor Twigg during the Fall '09 term at Binghamton.

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p2 - EECE 416/501 Fall 2009 Project 2 Introduction to the...

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