p3 - EECE 416/501 Fall 2009 Project 3 Device...

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Project 3 Due 10/20/2008 Fall 2009 Device Characterization and Model Parameter Extraction This project is to be completed in groups of 2. Academic Honesty Policy All students must adhere to the Student Academic Honesty Code of the University and the Watson School. The Electrical and Computer Engineering Department has adopted a standard policy to enforce these codes for course work violations. Category I violations result in a grade of 0 for the graded work plus a full letter grade reduction for the course. A Report of Category I Academic Dishonesty form is filed with the Provost's Office; if a prior report is already on file, the offense is automatically elevated to Category II. Category II violations result in at least a failing grade for the course plus any additional penalties determined by the Watson Academic Integrity Committee. Goal and General Description The purpose of this project is to characterize nFETs and pFETs in a particular process and to extract the relevant large signal model parameters. Since we do not have access to lab hardware, you will be performing this characterization using simulations. From these simulations, you will generate data files that can be analyzed in MATLAB. Based upon this analysis, you will extract the various parameters, such as κ , K, and V A , needed to calculate small signal values in later projects. There is no need to generate any layout. For this project, you will work in groups of 2 (or 3, depending upon course enrollment). How you divide the work is up to you, but it may be useful for one person to perform the nFET characterization and the other the pFET characterization. This will help ensure that both members understand the procedure for this project. However, all group members should review all of the data and analysis for accuracy and completeness. All members are also expected to contribute to the project summary. Procedure To begin, you will need to create new schematics for simulating the transistors. An example is shown to the left for the nFET characterization and below for a pFET configuration (many different circuit possibilities will yield the needed simulation results). Make the W and L values 180 μm such that the W/L ratio will be 1. 10/11/2009
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This note was uploaded on 06/30/2010 for the course EECE 501 taught by Professor Twigg during the Fall '09 term at Binghamton.

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p3 - EECE 416/501 Fall 2009 Project 3 Device...

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