{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Exam2_sol

# Exam2_sol - .SO MT 0 HS NAME EE315 EXAM#2(closed books FALL...

This preview shows pages 1–3. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: .SO MT, 0 HS NAME EE315 EXAM#2 (closed books) FALL 2004 Problem 1 Given the transfer characteristic of a digital logic inverter Show the following parameters in the ﬁgure and ﬁnd their values: a) VOH= 5 V b>vor= 025V c) Noise Margin HI= ‘2 \/ d) Noise Margin LO: 1 -/75 V Problem 2 Given a 4-bit summing ampliﬁer D/A converter below. It is known that VreFSV, R1=le, and the op—amp is powered by a 112V power supply. Find the maximum value of R2 that assures that the op— amp never saturates ,M. 1113+'2 21 3.3.0.) Vaas i VOMT’ 22( RI 275, A, ”Rudy XE! Vveé mummy: The low/963+ [absolute VQ/ue] Ou-+pu+ is emowfewa/ WM“ “H’i€ [Vt/791+ "y H H/ 56146? I .1. 1. ~-l—)\/ » v|2\$ ”92 (TL-14.22] +L/R‘ + 3712. re? [52 Vreg 42\$"— ~—Z————-—a 9Q, lz< _ M3 {22\$ ’ZgOﬂ I?” "' g, 103 1- 8:: a 0 (switch down) l 'err Problem 3 Design a CMOS Circuit to implement the following logic function: Y = A + BC 8129+“: A+gc 2 AER = 5,/E+E) Problem 4 Given the transfer characteristic of the Schrnitt trigger. The input signal is Vm=2+6sin(27t*500t). Sketch both Vin and Vout in the same ﬁgure. Problem 5 Given signals S, R, and Q for a clocked Set-Reset ﬂip-ﬂop. Sketch the clock signal C if it is known that its pulse width (duration of H1) is 5ns. Find frequency of the clock signal. "'72 20m; 102%:50MH5 I V 100 i 150 L0 - ...
View Full Document

{[ snackBarMessage ]}

### Page1 / 3

Exam2_sol - .SO MT 0 HS NAME EE315 EXAM#2(closed books FALL...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online