Lecture12a - Some TTL gates have tri-state output (when...

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Lecture 12. DIGITAL LOGIC Objectives: Topics: Describe characteristics of TTL and CMOS logic Design CMOS gates Describe operation of S-R flip-flops TTL Logic CMOS Logic S-R Flip-Flops
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Dynamic Performance Consider a BJT inverter V L v IN V H V H v OUT Cut off C.C.R. Satur. Drive the BJT into cutoff or saturation to output ‘1’ or ‘0’ What is the desired slope of the transfer characteristic? How to achieve this?
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Dynamic Performance (Cont’d) How fast can the gate switch if it drives capacitive load? a) Output switches to HI b) Output switches to LO t r and t f can be minimized if current i is large t r , t f -? R C limits i (R C is large) i is only a fraction of i C
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TTL Logic Family Built with 2 stages: input and output (totem-pole) Has a steep transfer characteristic, but also switches fast V L =0.2 v IN V H V H =3.8 v OUT d a b c Approximate transfer characteristic of a TTL inverter a) v IN =0, v OUT =3.8V b) v IN =0.4V, v OUT =3.8V c) v IN =1.1V, v OUT =3.1V d) v IN =1.2V, v OUT =0.2V
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Unformatted text preview: Some TTL gates have tri-state output (when used with a data bus) CMOS Logic Family v IN v OUT V OH V OH V OL a b slope=-1 NM NM CMOS gate drives another CMOS gate, hence the load is capacitive If we choose MOSFETs such that K N =-K P and V TRN =-V TRP , then V IH V IL CMOS Logic Gates a) NOR Gate A 1 1 B b) NAND Gate A 1 1 B n-side is exactly opposite to p-side CMOS Transmission Gates Bidirectional current can flow from A to B or from B to A- connects A to B when C=HI When C=LO, HI C = When C=HI, LO C = If A=0 (LO) If A=1 (HI) Transmission gates could be used in tri-state output circuits S-R Flip-Flops NOR Gate: 1 A 1 1 B Cross-coupling (feedback) between inputs and outputs gives memory capabilities S=0, R=0: If Q=1, , then = Q If Q=0, , then 1 = Q S=1, R=0: S=0, R=1: S=1, R=1:...
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Lecture12a - Some TTL gates have tri-state output (when...

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