chapter08sm

# chapter08sm - SOLUTIONS TO PROBLEMS FROM CHAPTER 8 8.1...

This preview shows pages 1–4. Sign up to view the full content.

SOLUTIONS TO PROBLEMS FROM CHAPTER 8 8.1. Figure P8.1. shows the I D - V GS characteristic for an NMOS with V DS =50 mV. It is known for this device that W= 10 µ m, L =0.5 µ m, and t ox =5 nm. a) Find the threshold voltage Since V DS =50 mV and L =0.5 µ m, the average field in the channel is 0.1 V/ µ m=1kV/cm and the device is not in the velocity saturation region. Thus the expression (Equation (8.4)) () ' 0 12 ox DS DS DG S GS T WC V V IV LV V µ θ ⎛⎞ =− ⎜⎟ +− ⎝⎠ T V can be used. The threshold is extrapolated from the linear region, and using Equation (8.8), 0.05 0.5 22 DS TT V VV V += = + Therefore V T =0.475V. b) Find 0 , the electron channel mobility at threshold. The slope of the linear region is about 160 µ A/(0.5V)=0.32mA/V. From Equation (8.7), we have ' 0 D ox DS GS dI WC V dV L = Anderson & Anderson 1 January 19, 2005 Solutions Chapter 8

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
C ox ' = ε ox t ox = 3.9 ( ) 8.85 × 10 14 F / cm () 5 × 10 7 cm = 6.9 × 10 7 F / cm 2 Solving for µ 0 we have 32 0 '7 2 0.5 0.32 10 / 460 10 6.9 10 / 0.05 D GS ox DS dI L dV A V cm WC V F cm V V s ⎛⎞ × == = ⎜⎟ × ⎝⎠ 8.2. A particular MOSFET process produces C =10 B ' -7 F/cm 2 and , and a threshold voltage of V I 0 = 4 × 10 20 A T =0.5V. For gate oxide thicknesses of 6.5 nm and 4 nm, find n and S . Which device is better, and why? For t ox =6.5 nm, C ox ' = ox t ox = 3.9 8.85 × 10 14 F / cm 6.5 × 10 7 cm = 5.3 × 10 7 F / cm n = 1 + C B ' C ox ' = 1 + 10 7 5.3 × 10 7 = 1.19 S = 2.3 kTn q = 71 mV / decade For the 4 nm oxide, =, and 8.63 10 / ox CF c m n = 1 + C B ' C ox ' = 1 + 10 7 8.63 × 10 7 = 1.12 S = 2.3 kTn q = 2.3 0.026 1.12 = 67 mV / decade The 4 nm device is better. The swing S is smaller, resulting in a sharper turn-on and thus permitting a reduced threshold voltage and a reduced power supply voltage and reduced power consumption. 8.3. a) Find W p / W n needed to match I Dsat for CMOS transistors if , lfn = 500 cm 2 / V s lfp =200 cm 2 /V·s, L= 0.5 µ m, and V GS - V T =2.6 V. Assume that s. 6 41 0 / sat vc m s From Figure 8.6, we want W p W n = 1.3 . b) Find V DSsat for the NMOS and the PMOS. Anderson & Anderson 2 January 19, 2005 Solutions Chapter 8
() 1 2 1 2 2 6 4 2 64 2 v 11 v 25 0 0 2 . 6 41 0 0.5 10 1 1 0 0 . 51 0 500 1.09 lfn GS T sat DSsat n nFET lfn sat nFET VV VL L cm cm V Vs s cm cm cm cm s V µ ⎡⎤ ⎛⎞ ⎢⎥ =+ ⎜⎟ ⎝⎠ ⎣⎦ × + ×× = (or one could read it off Figure 7.31) Similarly, 1 2 1 2 2 6 4 2 2 2 200 2.6 0 0.5 10 1 1 0 0 . 0 200 1.49 lfp GS T sat DSsat p pFET lfp sat pFET v vL cm cm V s cm cm cm cm s V × + = c) Adjust the length of the NFET to equalize the V DSsat ’s . What should the new W p W n be to keep the I Dsat ’s equal? We want to set V DSsat(n) to 1.49V. From Figure 7.31, the new channel length for the NFET should be about 1.2 µ m. Then to set the I Dsat’s equal, we set I Dsat ( n ) I Dsat ( p ) = 1 or ' ' 2 1 1 2 1 DSsatn n ox lfn GS T DSsatn lfn DSsatn nFET Dsat n nFET sat DSsatp Dsat p p ox lfp GS T Dsatp lfp DSsatp pFET pFET sat V WC V V V V L I Lv V I V V V V L −− + == + Since we have already adjusted the channel lengths to equalize the V DSsat ’s, we know that V DSsatn = V DSsatp and thus

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 06/30/2010 for the course EECE 332 taught by Professor Constable during the Spring '08 term at Binghamton.

### Page1 / 12

chapter08sm - SOLUTIONS TO PROBLEMS FROM CHAPTER 8 8.1...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online