Unformatted text preview: EE 477L Homework 4 Solutions Spring ’09 ● Nazarian
Name: _________________________________________ Assigned: Monday March 23, 2009 Due: Thursday April 2, at 9:30am (in class) Lecture 9:30 Score: ________ 1. Answer
There are two methods of delay calculation (ACC and DIFF) in chapter 6 slides. They are essentially the same; however, ACC avoids the integration by averaging the current which means it is less accurate. So, ACC should produce a higher delay value than DIFF. First consider ACC: ============== We compute Cload as follow: Compute CGB(P2) and CGB(N2) using parallel place capacitance: k ´e 4 ´ 8.85 ´1012 F / m CGB ( P2 ) = 0 0 WP LP = (12 ´106 m)(2 ´106 m) = 85 fF 9 tox 10 ´10 m
k ´e 4 ´ 8.85 ´1012 F / m CGB ( N 2 ) = 0 0 WN LN = (6 ´106 m)(2 ´106 m) = 42.5 fF 9 tox 10 ´10 m Compute Cl using parallel place capacitance:
k ´e 4 ´ 8.85 ´1012 F / m CI = 0 0 WI LI = (30 ´106 m)(1´106 m) = 106 fF 9 tox 10 ´10 m with CDB(P1) = CDB(N1) = 50 fF, now we can compute Cload:
Cload = CGB ( P2 ) + CGB ( N 2 ) + CDB ( P ) + CDB ( N1 ) + CI = 333.5 fF 1 when the input goes from high to low, the output changes from low to high; hence, we use the following formula to compute tdr or tPLH(Propagation delay Low to High): C (V V ) tdr = t PLH = load 50% OL I avg , LH 2 when Vin=VOL and Vout=V50% the PMOS transistor is in linear region and for other case the PMOS is in saturation region, so we have:
2ù bp é 2(V (VGS _ sat  VT )2 GS _ lin  VT )VDS _ lin  (VDS _ Lin ) û + 2ë 2 I avg , LH = 2 k ´ e Wp 4 ´ 8.85 ´1012 12 where b p = m p ´ 0 0 ´ = 250 ´104 ´ ´ = 5.31´1010 9 tox Lp 2 10 ´10 where : I avg , LH = I dsp (Vin = VOL ,Vout = V50% ) + I dsp (Vin = VOL ,Vout = VOL ) bp 5.31´1010 é 5.31´1010 2(5 + 1) ´ 2.5  (2.5)2 ù + (5 + 1)2 ë û 2 2 I avg , LH = = 39493.125 A 2 333.5 ´ (2.5  0) t PLH = = 211 pS 39493.125 1 Now consider DIFF: ============== In DIFF method we use the following formula to compute tdr or tPLH(Propagation delay Low to High): tdr = t PLH = æ ö 2  VT , P  4(VDD   VT , P ) Cload + ln(  1) ÷ ç ÷ VDD b p (VDD   VT , P ) ç (VDD   VT , P ) è ø k ´ e Wp 4 ´ 8.85 ´1012 12 where b p = m p ´ 0 0 ´ = 250 ´104 ´ ´ = 5.31´1010 9 tox Lp 2 10 ´10 t PLH = 333.5 ´1015 5.31´10
10 æ 2 ´1 ö 4(5  1) + ln(  1) ÷ = 202 pS ç 5 ´ (5  1) è (5  1) ø As you can see the computed delay using DIFF is less than ACC 2. Answer
(Wire capacitance) Assume a wire fringing capacitance to substrate of 23.0 aF/um (af = 1e18F), and wire to substrate capacitance of 8.0e18aF/um2, an ohms/sq value of 0.08, and a repeater delay of 50ps. For a wire with length = 10,000 um and width = 0.4um, how many repeater stations should be added to the wire to reduce the wire delay to a minimum? Use the expression “0.9 × Rtotal × Ctotal” for estimated wire delay. When computing the fringing capacitance contribution, assume the given capacitance value includes both sides of the wire. Show your work. The total capacitance Ctotal is given by the sum of the fringe and substrate capacitance. Cfringe = 23aF/um × 10000um = 0.23pF and Csub = (0.4×10000) × 8af/um = 32fF Thus, Ctotal = Cfringe + Csub = 0.262pF Rtotal = Rsheet× (L/W) = 0.08× (10000/0.4) = 2kΩ Estimated wire delay τwire = 0.9×Rtotal×Ctotal = 0.9 × 0.262pF × 2kΩ = 471.6ps Using 1 buffer, C = Ctotal/2 and R = Rtotal/2. Thus, delay = 2×{0.9 (.262pF/2)(2kΩ/2)} + 50ps = 286ps. Using 2 buffers, C = Ctotal/3 and R = Rtotal/3. Thus delay = 3×{0.9(.262pF/3)(2kΩ/3)}+2×50ps = 257ps. Using 3 buffers, C = Ctotal/4 and R = Rtotal/4. Thus delay = 4×{0.9 (.262pF/4)( 2kΩ/4)} + 3*50ps = 268ps. Since the minimum delay is obtained at 2 inverters, that will be the number of inverters required. 2 3. Answer 3 4 Therefore the delay times (tdr or tPLH and tdf or tPHL) are found as 5 4. Answer
We have two cases when the input of the first inverter goes from (1) low to high and (2) high to low. 5. Answer
Draw the circuits for the attached NAND and NOR gates. Note that the output of the inverter splits into four lines, and each line is attached to a PMOS and an NMOS transistor which means four CGB of type PMOS and four CGB of type NMOS contribute as part of the CLOAD in the propagation delay of the inverter. You may also model each fanout line with a PMOS and NMOS with a CMOS inverter and therefore the output of the inverter with four inverters (each gate is 2 inverters.) I did not specify whether to allow one interconnect capacitance per gate or per input, so: One Possible Answer: Using one interconnect capacitance per gate: Low to high transition: The other Possible Answer: 6 6. Answer 7 7. Answer
The wire width is 1.2 mm so the wire is 5000 mm/1.2 mm = 4167 squares in length. The total resistance is (0.08W/sq)•(4167sq) = 333 W. The total capacitance is (0.2fF/mm)•(5000 mm) = 1 pF. 8. Answer
A unit inverter has a 4l = 1.2 mm wide nMOS transistor and an 8l = 2.4 mm wide pMOS transistor. Hence the unit inverter has an effective resistance of (2.5 kW•mm)/(0.36 mm) = 6.9 kW and a gate capacitance of (1.2 mm + 2.4 mm)•(2 fF/mm) = 7.2 fF. The Elmore delay is tpd = (690 W)•(500 fF) + (690 W + 330 W)•(500 fF +14 fF) = 0.72 ns. 9. Answer
We use the following equation to compute the delay for each pair: t DN = å C j å Rk
j =1 k =1 N j Equ.(6.63) from textbook t AB = C ´ ( R) + 2C ´ ( R + 3R) + C ´ ( R + 3R + 5R) + C ´ ( R + 3R + 5R + 2 R) +
3C ´ ( R + 3R + 5R + 2 R + 2 R) + C ´ ( R + 3R + 5R + 2 R) + C ´ ( R + 3R) + C ´ ( R + 3R) + 4C ´ ( R + 3R) + 2C ´ ( R + 3R) = 111RC t AC = C ´ ( R) + 2C ´ ( R + 3R) + C ´ ( R + 3R + R) + 4C ´ ( R + 3R + R + 3R) +
2C ´ ( R + 3R + R + 3R + 2 R) + C ´ ( R + 3R + R) + C ´ ( R + 3R) + C ´ ( R + 3R) + 3C ´ ( R + 3R) + C ´ ( R + 3R) = 95RC The computed delays using Elmore delay model show that the delay from Node A to Node C is less than the delay from Node A to Node B. (Computations for resistanceoriented is same as capacitanceoriented ) 8 ...
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This note was uploaded on 07/21/2010 for the course EE 477 taught by Professor Shahinnazarian during the Spring '09 term at USC.
 Spring '09
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