{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

HW_6 - EE 477L Homework and Solution 6 Spring 09 Nazarian...

Info icon This preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 477L Homework and Solution 6 Spring ’09 Nazarian Name: _________________________________________ Lecture 9:30 Assigned: Thursday April 9, 2009 Score: ________ 1. Size the transistors in a 5-input NAND gate so that the worst case rise and fall times are equal, assuming the smallest transistors are unit width and unit length. Label the inputs and explain the combination of input changes that gives worst case rise and fall times. Solution: 4.3 n p b b = and for the smallest transistor (PMOS) we have W p =4 l and L p =2 l and we take L p =L n =2 l ; =1.16*4 l =4.6 l (5 l is used)
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2. Compute the gate capacitance of an NMOS transistor that has width dimensions 3 times minimum size and minimum length. Solution: NMOS: W n =3*3 l and L n =2 l =8.85e-14*3.9*3*3 l *2 l /57e-10 =1.569fF 3. Consider the circuit of figure below: (a) What is the logic function implemented by the CMOS transistor network? (b) What are the input patterns that give the worst case t pHL and t pLH . State clearly what the initial input patterns are and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the
Image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}