CHAPTER5InverterStatic-EE477-Nazarian-Spring09

CHAPTER5InverterStatic-EE477-Nazarian-Spring09 - University...

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University of Southern California OS VLSI Circuit Design: MOS VLSI Circuit Design: MOS Inverter: Static Characteristics Nazarian EE477L – Spring 2009
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Introduction Ideal Inverter Basic principles of design and analysis of an inverter can be applied to more complex gates Positive voltage convention: Boolean (or logic) value of 1 = high voltage of V DD Boolean (or logic) value of 0 = low voltage of 0 Inverter threshold voltage V M (don t confuse it with transistor threshold voltage V T ) V M = V DD /2 DC Voltage Transfer Characteristics (VTC) of an ideal inverter Nazarian/EE477L/Spring 2009 2
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Ideal Inverter Threshold Voltage V M For 0 V in < V M = V DD /2 V out = V DD (logic 1 ) or V 0 (logic For V M < V in V DD V out = 0 (logic 0 ) 0 V in <V M is interpreted as a logic 0 terpreted s gic V M < V in V DD is interpreted as a logic 1 Nazarian/EE477L/Spring 2009 3
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Voltage Transfer Characteristic (VTC) of an NMOS Inverter V in is V GS ut V S V out is V DS V SB = 0 The circuit connected to the utput ode an e presented output node can be represented as a lumped capacitance C out If DC gate current is negligible I out (i.e., no load current) I out = 0 by KCL: I D (V in ,V out )=I L (V L ) By analytically solving this y yy g equation for various V in we can find VTC V SB =0 Nazarian/EE477L/Spring 2009 4 General circuit structure of an nMOS inverter
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VTC There are two critical voltage points for which: dV out /dV in =-1 V OH : Max output voltage when output level is logic 1 in utput oltage hen utput vel gic V OH = f(V OL )=V OL L = V H = H V OL : Min output voltage when output is level logic 0 V OL f(V OH ) V OH V IL : Maximum input voltage which can be interpreted as logic 0 V IH : Minimum input voltage which can be interpreted as logic 1 verter reshold oltage Inverter threshold voltage (V M ): defined as the point where V in =V out (transition voltage) V OL Nazarian/EE477L/Spring 2009 5
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VTC (Cont.) Lowest available voltage in system (i.e. 0) V in V IL V in is interpreted as logic 0 input ighest available voltage in system V IH V in Highest available voltage in system V in interpreted as logic 1 input Lowest available voltage in system V out V OL V out is interpreted as logic 0 output V OH V out Highest available voltage in system interpreted as logic utput V out is interpreted as logic 1 output Nazarian/EE477L/Spring 2009 6
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Tolerance Inverter s ability to interpret a range as logic 0 or 1 allows digital circuits to operate with certain lerance to signal perturbations (noise) tolerance to signal perturbations (noise) Noise can be an unwanted inductive or capacitive coupling from neighboring lines, or outside-of-the- system interference Nazarian/EE477L/Spring 2009 7
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Noise Immunity and Noise Margins Consider the following circuit (all inverters are identical)
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This note was uploaded on 07/21/2010 for the course EE 477L taught by Professor Parker during the Spring '08 term at USC.

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CHAPTER5InverterStatic-EE477-Nazarian-Spring09 - University...

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