ChapterIX-DynamicLogic-EE477-Nazarian-Spring09

# ChapterIX-DynamicLogic-EE477-Nazarian-Spring09 - University...

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University of Southern California Dynamic Logic Circuits Nazarian EE477L – Spring 2009 Nazarian/EE477L/Spring 2009

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Dynamic Logic Dynamic logic circuits depend on temporary (transient) storage of charge in parasitic node capacitances need periodic updating of internal node voltage vels levels require periodic clock signals in order to control charge refreshing use a common clock signal in order to enable us to synchronize the operations of various circuit blocks have smaller area than the static logic implementation Nazarian/EE477L/Spring 2009 2
Example 9.1 – Dynamic D-latch Consider the dynamic D-latch circuit shown below The parasitic input capacitance C x plays an important role in e ynamic peration f is ircuit the dynamic operation of this circuit When CK=1, MP turns on, C x is either charged up, or charged down through the pass transistor MP, depending on the input ) oltage vel he utput ) ssumes e ame gic vel (D) voltage level. The output (Q) assumes the same logic level as the input When CK=0, MP is off and C x is isolated from D. The amount of harge tored uring e revious ycle etermines charge stored in C x during the previous cycle determines V Q Node X is also called a soft node Nature of soft node makes the dynamic circuit more vulnerable to single-event upsets (SEQs) caused by α -particleo rcosmicray hits in integrated circuits Nazarian/EE477L/Spring 2009 3

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Example 9.1 (Cont.) Consider V DD =5 V and assume that the VTC’s of both inverters are identical, V OL =0V, V IL =2.1V, V IH =2.9V, V OH =5.0V ,a n d n = V T,n 0.8V When CK=1 and V in =V OH =5 V: MP is conducting and C x ischargeduptoalog ich igh vel level NMOS is a poor conductor for logic “1” and its output voltage V x will be lower than V OH V x =5.0-0.8=4.2V (which is more than V IH of the first inverter, therefore V Q’ is very close to V OL =0V Consequently Q becomes a logic “1”, i.e., V =V D Q DD Nazarian/EE477L/Spring 2009 4 Q
Example 9.1 (Cont.) When CK=0 (MP is off) Initially X is high and Q is high. V X starts to drop because of charge leakage from the soft node To keep Q at logic “1”, the voltage level at node X cannot be allowed to drop lower than V IH =2.9 V lock ignal an e ept w r s ng s kes r Clock signal can be kept low for as long as it takes for V X to drop from 4.2V to 2.9V due to charge leakage. To avoid an erroneous output, the charge stored in C X must be restored or refreshed to its original level before V X reaches 2.9V This example shows the dynamic-charge storage principle in Q’ Nazarian/EE477L/Spring 2009 5 D-latch is quite feasible for preserving output state during inactive clock phase, assuming leakage currents are small

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Basic Principle of Pass Transistor Circuits The two possible operations when clock is high: Logic “1” transfer (charging up C x to a logic- high level) Logic “0” transfer (charging down C x to a logic- w level) low level) When CK=0, MP ceases to conduct and the charge stored in C continues to determine the output level x
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## This note was uploaded on 07/21/2010 for the course EE 477L taught by Professor Parker during the Spring '08 term at USC.

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ChapterIX-DynamicLogic-EE477-Nazarian-Spring09 - University...

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