ChapterVI-CMOSSwitchingChar&amp;Interconnect-EE477-Nazarian-Spring09

# ChapterVI-CMOSSwitchingChar&Interconnect-EE477-Nazarian-Spring09

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U i it f S th C lif i University of Southern California MOS Inverter Switching Characteristics and Interconnect Effects: Logic Cell Delay Calculation Methods Nazarian EE477L – Spring 2009 Nazarian/EE477L/Spring 2009

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Outline Background on CMOS logic cell delay calculation and timing analysis Cell delay calculation methods Average capacitance current (ACC) • Differential equation (DIFF) Differential equation (DIFF) Current Source Model (CSM) (will be covered in the d f th t i l t i end of the semester as a special topic Nazarian/EE477L/Spring 2009 2
CMOS VLSI Chips A VLSI chip has two main components: logic components and the wires that connect the logic A wafer, which is about 14 inches, is cut to hundreds of chips. Chips can have up to nine layers of wires, between layers contacts are used with a billion transistors and a mile of wires As a designer you would ask: How do I calculate the circuit speed? Does the design meet a As a designer you would ask: How do I calculate the circuit speed? Does the design meet a given timing requirement?!! How fast can I run the design?!!! Why Model is required? For fast simulation, For creating optimal design, Real design will be always more costly and time consuming to analyze Nazarian/EE477L/Spring 2009 3 So model is used to simulate the system before actual implementation

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Introduction Timing Analysis is a key step in “Design Flow” Power and noise analysis, optimization, …. To perform timing analysis delay models are required for both wire To perform timing analysis, delay models are required for both wire and logic cell For logic cell the delay model, should account for its loading For interconnect the delay model should account for its driver A transistor level simulator, such SPICE is very accurate in calculating circuit timing information, but too slow to be employed in most of the stages of design of such circuit In Static Timing Analysis, slowest and fastest timings are calculated and propagated all the way to the primary output A D C G 1 G 2 B Nazarian/EE477L/Spring 2009 4
Static Timing Analysis Example: Worst case analysis: Nazarian/EE477L/Spring 2009 5

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