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Prob15

# Prob15 - PI5—15.nb 1 I P15.15 NMOS inverter with...

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Unformatted text preview: PI5—15.nb 1 I P15.15 - NMOS inverter with resistive load Since the algebra for this problem gets messy, it is easier to solve using the computer. Therefore, we show here how to solve it using Mathematica. The basic procedure is straightforward however, and can be done by hand or using any other program. We want to plot the VTC of a resistively loaded NMOS inverter and check the break points for ﬁnding VIL, VIH, VOL, and VOH. First enter the given data: In[165].’= VDD = 5. Out[165]= 5. In[166]:= K = 25. *10"—6 Out[166]= 0. 000025 In[167]:= RD = 50. *10"3 Out[l67]= 50000 . In[l68]:= Vth = 0.8 Out[168]= O . 8 There are three regions of operation for the device. For VI = VGS < Vth, the transistor is cutoff and V0 = VDD. When VI > Vth, the device may be saturated or linear depending on the value of VDS = VO. When V1 is just barely larger than Vth, VO will be high and the device will be saturated. Therefore, we ﬁrst provide the equation for the drain current when the device is saturated. In[169]:= IDsat[VI__] :=K*(VI-Vth)"2 Independent of the mode the transistor is in, the output voltage is given by VO = VDD - ID*RD. If we substitute the equation given above for ID into this, we have an equation for V0 when the transistor is saturated. In[170] := VOsat [VI__] := VDD - RD * IDsat [VI] We need to know the breakpoint between the device being saturated and linear. The break occurs when VO = VI - Vth, so use that value for V0 in the equation derived from the circuit and set it equal to the drain current as determined by the transistor. In[171]:= Solve[IDsat[VI] == (VDD-VI +Vth) IRD, VI] Out[17l]= {{VI —) —l.63961}, {VI —>2.4396l}} We must, of course, take the positive root. So, the transistor is in the linear regime when VI > 2.43961 V. When the transistor is in the linear regime, the drain current is given by: In[172]:= IDlin[VI__, vo_] := K (2* (VI -vth) *vo -vo"2) PI5—15.nb Because this current is a function of VI and V0, we can't simply plug it into the circuit equation and have our answer. We must solve simultaneous equations. We can, however, use Mathematica to algebraically solve the equations for us. The commands to do this are given at the end of this notebook. There are two possible solutions and we chose the proper one by trying both of them in the transfer characteristic plotted below. If you do this, it is obvious which one is correct. The solution is: 1 In[l73]:= VOlin[VI__] := (1 +2KRDVI -2KRDVth—‘\/—4KRDVDD+ (—1 -2KRDVI+2KRDVth)2) 2KRD Now we can write an equation for V0 that uses the three different regions of operation: for V1 < Vth, VO = VDD, for Vth < VI < VIbreak, VO=VOsat, and for VI>VIbreak, VO=VOlin. In[l 741,-: v0[v1_] := If [v1 >Vth, If [v1 < 2.439607805437114‘ , VOsat[VI] , VOlin[VI] ] , vnn] We can now plot the transfer characteristic. In[l75]:= Plot[VO[VI], {V1, 0, 5}, AspectRatio -> 1] 5 l 2 3 4 5 Out[175]= - Graphics - Now let's solve for where the derivative of V0 with respect to V1 is equal to -1 in the region where the transistor is linear. We differentiate V0 with respect to V1 and set the derivative equal to -1: In[176]:= Solve[D[V01:i.n[VI], VI] == -1, VI] Out[176]= {{VI —-> 2.7094}} So, VIH = 2.71 V. The corresponding value of V0 is VOL and is: In[177] : VOL = VOlin[2 . 7094010767585033 ‘] Out[177]= 1.1547 Now solve for the point at which the slope is equal to -1 for the region where the transistor is in saturation: PI5-I5.nb In[178]:= Solve[D[VOsat[VI], VI] == -1, VI] Out[178]= {{VI ~> 1.2}} This answer tells us that VIL = 1.2 V. The corresponding value of V0 is VOH and is: In[179]:= vou = VOsat[1.2‘] Out[179]= 4.8 I Here are the commands to algebraically solve the equations when the transistor is in the linear regime. We put these commands at the end because you must ﬁrst clear the numeric values of the variables if you want to see the results algebraically. In[180] := C1ear[K, Vth, RD, VDD] First, eliminate the variable IDlin from the two equations for ID. In[181] := E1iminate[{IDlin == K (2 * (v1 — Vth) *vo — voe2) , IDlin == (VDD — vo) /RD} , IDlin] Out[181]= VDD == VO (1 + 2 KRDVI —KRDVO— 2 KRDVth) && RD qe 0 Now solve the resulting equation for V0. In[182]:= Solve[VDD == vo (1+2KRDVI-KRDVO—2KRDVth), v0] Out[182]= {{vo —> 2 K RD (1+2KRDVI-2KRDVth—\/——4KRDVDD+ (~l—2KRDVI+2KRDVth)2)}, } {vo—> (1+2KRDVI~2KRDVth+\/—4KRDVDD+ (—1-2KRDVI+2KRDVth)2) ZKRD I (b) The resulting noise margins are: NMH = VOH - VIH = 2.1 V NML = VIL - VOL = 0.05 V <-- note that this is terrible! ...
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Prob15 - PI5—15.nb 1 I P15.15 NMOS inverter with...

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