Chapter04 - Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C Jaeger Travis N Blalock Jaeger\/Blalock Microelectronic Circuit

Chapter04 - Chapter 4 Field-Effect Transistors...

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Jaeger/Blalock 4/25/07 Microelectronic Circuit Design, 3E McGraw-Hill Chap 4-1 Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock
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Jaeger/Blalock 4/25/07 Microelectronic Circuit Design, 3E McGraw-Hill Chap 4-2 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i-v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Learn basic structure and mask layout for MOS transistors and circuits. Explore MOS device scaling Contrast 3 and 4 terminal device behavior. Describe sources of capacitance in MOSFETs. Explore FET modeling in SPICE.
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Jaeger/Blalock 4/25/07 Microelectronic Circuit Design, 3E McGraw-Hill Chap 4-3 MOS Capacitor Structure First electrode- Gate: Consists of low-resistivity material such as metal or polycrystalline silicon Second electrode- Substrate or Body: n - or p -type semiconductor Dielectric-Silicon dioxide:stable high-quality electrical insulator between gate and substrate.
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Jaeger/Blalock 4/25/07 Microelectronic Circuit Design, 3E McGraw-Hill Chap 4-4 Substrate Conditions for Different Biases Accumulation V G <<V TN Depletion V G <V TN Inversion V G >V TN Accumulation Depletion Inversion
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Jaeger/Blalock 4/25/07 Microelectronic Circuit Design, 3E McGraw-Hill Chap 4-5 Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate MOS capacitance is non- linear function of voltage. Total capacitance in any region dictated by the separation between capacitor plates. Total capacitance modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance.
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Jaeger/Blalock 4/25/07 Microelectronic Circuit Design, 3E McGraw-Hill Chap 4-6 NMOS Transistor: Structure 4 device terminals: Gate (G), Drain(D), Source (S) and Body(B). Source and drain regions form pn junctions with substrate. v SB , v DS and v GS always positive during normal operation. v SB always < v DS and v GS to reverse bias pn junctions
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Jaeger/Blalock 4/25/07 Microelectronic Circuit Design, 3E McGraw-Hill Chap 4-7 NMOS Transistor: Qualitative I-V Behavior V GS <<V TN : Only small leakage current flows. V GS <V TN : Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. V GS >V TN : Channel formed between source and drain. If v DS >0,, finite i D flows from drain to source.
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  • Spring '09
  • Blalock
  • Transistor, Microelectronic Circuit Design

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