tutLN6soln

tutLN6soln - FIT1001 Memory Solutions to FIT1001 Tutorials...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: FIT1001 Memory Solutions to FIT1001 Tutorials for LN6 Memory – Caches and Virtual Memory * Exercise 1 Memory hierarchy Describe the execution of a program through the memory hierarchy. Begin by supposing that the program is only on disk. Consider both instructions and data. SOLUTION Let’s assume that the data is still on disk. • First look in the cache for the first instruction in the program → MISS. • Next look in main memory → PAGE or SEGMENT FAULT. Copy the page or segment containing this line of the program into memory, and then copy the line into the cache. • Now, this line may reference a datum. – If the virtual memory is segmented, the datum will be in the same segment as the program, but it won’t be in the cache → MISS, and the datum is copied into the cache. – If the virtual memory is paged, then the datum may be in a different page, and the above process repeats. * Exercise 2 Temporal and spatial locality Give an example that illustrates how the cache exploits the principles of temporal locality and spatial locality. SOLUTION (from the lecture) • Temporal locality – the instructions in a loop all reside in the cache (they are being used over and over within a short time). • Spatial locality – accessing the elements of an array, and also the instructions in a loop. Both are examples of words that are next to each other, and will appear in the cache next to each other. In both examples, presence in the cache means that this information will be accessed quicker than if it were in main memory. * Exercise 3 Caches – Effective Access Time A computer has a two-level cache. Suppose that 80% of the memory references hit on the first level cache, 15% on the second level, and 5% miss. The access times are 5 nsec, 15 nsec and 60 nsec respectively. What is the effective access time? SOLUTION . 8 × 5 + 0 . 15 × 15 + 0 . 05 × 60 = 9 . 25 nsec 1 * Exercise 4 Directly-mapped cache Consider the diagram for a directly-mapped cache presented below. Assume a 32-bit archi- tecture and 4 GB of word-addressable memory....
View Full Document

This note was uploaded on 08/15/2010 for the course FIT 1001 taught by Professor Egerton during the Three '10 term at Monash.

Page1 / 5

tutLN6soln - FIT1001 Memory Solutions to FIT1001 Tutorials...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online