bzip_output_inst_fetch_2

bzip_output_inst_fetch_2 - This is the output file after...

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Sheet1 Page 1 This is the output file after running BZIP2 benchmark program on a processor with fetch,decode, execute and commit 2 instruction per cycle sim-outorder: SimpleScalar/PISA Tool Set version 3.0 of November, 2000. Copyright (c) 1994-2000 by Todd M. Austin. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use only. sim: command line: /auto/home-scf-10/ee557d/sscalar/sim-outorder -config test2.config -redir:sim test2.out bzip2 input.progra m sim: simulation started @ Thu Mar 25 19:24:51 2010, options follow: sim-outorder: This simulator implements a very detailed out-of-order issue superscalar processor with a two-level memory system and speculative execution support. This simulator is a performance simulator, tracking the latency of all pipeline operations. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim test2.out # redirect simulator output to file (non-interactive only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 100000000 # maximum number of inst's to execute -fastfwd 300000000 # number of insts skipped before timing starts # -ptrace <null> # generate pipetrace, i.e., <fname|stdout|stderr> <range> -fetch:ifqsize 2 # instruction fetch queue size (in insts) -fetch:mplat 3 # extra branch mis-prediction latency -fetch:speed 1 # speed of front-end of machine relative to execution core -bpred 2lev # branch predictor type {nottaken|taken|perfect|bimod|2lev|comb} -bpred:bimod 2048 # bimodal predictor config (<table size>) -bpred:2lev 16 256 4 0 # 2-level predictor config (<l1size> <l2size> <hist_size> <xor>) -bpred:comb 1024 # combining predictor config (<meta_table_size>) -bpred:ras 4 # return address stack size (0 for no return stack) -bpred:btb 64 4 # BTB config (<num_sets> <associativity>) # -bpred:spec_update <null> # speculative predictors update in {ID|WB} (default non-spec) -decode:width 2 # instruction decode B/W (insts/cycle) -issue:width 2 # instruction issue B/W (insts/cycle) -issue:inorder false # run pipeline with in-order issue -issue:wrongpath true # issue instructions down wrong execution paths -commit:width 2 # instruction commit B/W (insts/cycle) -ruu:size 32 # register update unit (RUU) size -lsq:size 16 # load/store queue (LSQ) size -cache:dl1 dl1:128:32:4:l # l1 data cache config, i.e., {<config>|none} -cache:dl1lat 2 # l1 data cache hit latency (in cycles) -cache:dl2 ul2:2048:64:8:l # l2 data cache config, i.e., {<config>|none}
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Sheet1 Page 2 -cache:dl2lat 6 # l2 data cache hit latency (in cycles) -cache:il1 il1:128:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2|none} -cache:il1lat
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bzip_output_inst_fetch_2 - This is the output file after...

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