cachel14

cachel14 - CACTI 5.3 Normal Interface Cache Size (bytes)...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: CACTI 5.3 Normal Interface Cache Size (bytes) Detailed Interface Line Size (bytes) Pure RAM Interface Associativity FAQ Nr. of Banks Technology Node (nm) Read/Write Ports Read Ports Write Ports Single Ended Read Ports Nr. of Bits Read Out Change Tag No Yes Nr. of Bits per Tag Type of Cache Normal Serial Fast Temperature (300-400 K, steps of 10) RAM cell/transistor type in data array (choose ITRS transistor for SRAM cell) ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM Peripheral and global circuitry transistor type in data array ITRS-HP ITRS-LSTP ITRS-LOP RAM cell/transistor type in tag array ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM (choose ITRS transistor for SRAM cell) COMM-DRAM Peripheral and global circuitry transistor type in tag array ITRS-HP ITRS-LSTP ITRS-LOP Interconnect projection type Aggressive Conservative Type of wire outside mat Semi-global Global Cache Parameters: Number of banks:1 Total Cache Size (bytes):8192 Size in bytes of bank:8192 Number of sets per bank:128 Associativity:2 Block Size (bytes):32 Read/Write Ports per bank:0 Read Ports per bank:1 Write Ports per bank:1 Technology Size (nm):32 Vdd:0.9 Access time (ns): 0.384814376034 Random cycle time (ns):0.277991126001 Multisubbank interleave cycle time (of data array) (ns):0.0923731979874 Total read dynamic energy per read port(nJ): 0.0124056546266 Total read dynamic power per read port at max freq (W): 0.044626081433 Total standby leakage power per bank (W): 0.00731759459181 Refresh power (percentage of standby leakage power): 0.0 Total area (mm^2): 0.117002543779 DRAM array refresh interval (microseconds):0.0 DRAM array availability (percentage):0.0 Best number of wordline segments (data): 2 Best number of bitline segments (data): 4 Best number of sets per wordline (data): 1.0 Best degree of bitline muxing (data): 1 Best degree of sense-amp level 1 muxing (data): 2 Best degree of sense-amp level 2 muxing (data): 2 Best number of wordline segments (tag): 2 Best number of bitline segments (tag): 4...
View Full Document

This note was uploaded on 08/15/2010 for the course EE 441 taught by Professor Neely during the Spring '08 term at USC.

Page1 / 6

cachel14 - CACTI 5.3 Normal Interface Cache Size (bytes)...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online