l2unifiedcache

l2unifiedcache - CACTI 5.3 Normal Interface Detailed...

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CACTI 5.3 Normal Interface Cache Size (bytes) Detailed Interface Line Size (bytes) Pure RAM Interface Associativity FAQ Nr. of Banks Technology Node (nm) Read/Write Ports Read Ports Write Ports Single Ended Read Ports Nr. of Bits Read Out Change Tag No Yes Nr. of Bits per Tag Type of Cache Normal Serial Fast Temperature (300-400 K, steps of 10) RAM cell/transistor type in data array (choose ITRS transistor for SRAM cell) ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM COMM-DRAM Peripheral and global circuitry transistor type in data array ITRS-HP ITRS-LSTP ITRS-LOP RAM cell/transistor type in tag array ITRS-HP ITRS-LSTP ITRS-LOP LP-DRAM
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SRAM cell) COMM-DRAM Peripheral and global circuitry transistor type in tag array ITRS-HP ITRS-LSTP ITRS-LOP Interconnect projection type Aggressive Conservative Type of wire outside mat Semi-global Global Cache Parameters: Number of banks:1 Total Cache Size (bytes):1048576 Size in bytes of bank:1048576 Number of sets per bank:2048 Associativity:8 Block Size (bytes):64 Read/Write Ports per bank:0 Read Ports per bank:2 Write Ports per bank:2 Technology Size (nm):32 Vdd:0.9 Access time (ns): 2.52576221006 Random cycle time (ns):0.367527005988 Multisubbank interleave cycle time (of data array) (ns):1.10582892683 Total read dynamic energy per read port(nJ): 0.941462269813 Total read dynamic power per read port at max freq (W): 2.56161385279 Total standby leakage power per bank (W): 1.93570975828 Refresh power (percentage of standby leakage power): 0.0 Total area (mm^2): 17.1122385614 DRAM array refresh interval (microseconds):0.0 DRAM array availability (percentage):0.0 Best number of wordline segments (data): 32 Best number of bitline segments (data): 8 Best number of sets per wordline (data): 1.0 Best degree of bitline muxing (data): 1 Best degree of sense-amp level 1 muxing (data): 8 Best degree of sense-amp level 2 muxing (data): 1 Best number of wordline segments (tag): 2 Best number of bitline segments (tag): 8
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This note was uploaded on 08/15/2010 for the course EE 441 taught by Professor Neely during the Spring '08 term at USC.

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l2unifiedcache - CACTI 5.3 Normal Interface Detailed...

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