realEstimator_mod_1

realEstimator_mod_1 - Name Value Description seed 0 Random...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Name Value Description seed 0 Random number generator fetch:ifqsize 1 Instruction fetch queue size fetch:mplat 3 extra branch mis-perdiction latency bpred 2lev branch predictor type (nottaken|taken|perfect|bimod|2lev) bpred:bimod 256 bimodal predictor BTB size bpred:2lev ll1size 64 2-level predictor config l1size param bpred:2lev l2size 256 2-level predictor config l2size param bpred:2lev hist_size 4 2-level predictor config hist_size param decode:width 1 instruction decode B/W (insts/cycle) issue:width 1 instruction issue B/W (insts/cycle) issue:inorder false run pipeline with in-order issue issue:wrongpath true issue instruction down wrong execution paths ruu:size 32 register update unit (RUU) size lsq:size 16 load/store queue (LSQ) size cache:dl1 128 l1 data cache config cache:dl1 32 l1 data cache config cache:dl1 4 l1 data cache config cache:dl1 l l1 data cache config cache:dl1lat 1 l1 data cache hit latency (in cycles) cache:dl2 2048 l2 data cache config cache:dl2 64 l2 data cache config cache:dl2 8 l2 data cache config cache:dl2 l l2 data cache config cache:dl2lat 6 l2 data cache hit latency (in cycles) cache:il1 128 l1 inst cache config cache:il1 32 l1 inst cache config cache:il1 2 l1 inst cache config cache:il1 l l1 inst cache config cache:il1lat 1 l1 inst cache hit latency (in cycles) cache:il2 2048 l2 inst cache config cache:il2 64 l2 inst cache config cache:il2 8 l2 inst cache config cache:il2 l l2 inst cache config cache:il2lat 6 l2 inst cache hit latency (in cycles) cache:flush false flush caches on system calls cache:icompress false convert 64-bit inst address to 32-bit inst equivalence mem:lat 150 memory latency first_chunk mem:lat 50 memory latency inter_chunk mem:width 8 memory access bus width (in byte) tlb:itlb 64 instruction TLB config tlb:itlb 4096 instruction TLB config tlb:itlb 4 instruction TLB config tlb:itlb l instruction TLB config tlb:dtlb 64 data TLB config tlb:dtlb 4096 data TLB config tlb:dtlb 4 data TLB config tlb:dtlb l data TLB config tlb:lat 150 inst/data TLB miss latancy res:ialu 2 total number of integer ALUs available res:imult 1 total number of integer multiplier/dividers available res:memport 2 total number of memory system ports available (to CPU) res:fpalu 2 total number of floating point ALUs available res:fpmult 1 total number of floating point multiplier/dividers available bugcompat false operate in backward-compatible bugs mode (for testing only) Comment ignored for complexity estimation fetch band width ignored for complexity estimation select the type of the branch prediction. At 2lev not specified if Pag or Pap number of BTB entries size of the 1st level table size of the 2nd level table pattern width in bits decode band width issue band width ignored for complexity estimation ignored for complexity estimation number of entries in the Register Update Unit number of entries in the Load Store Queue (LSQ) number of sets byte per line associativity replacement strategy (only LRU implemented) latency is ignored for complexity estimation...
View Full Document

This note was uploaded on 08/15/2010 for the course EE 441 taught by Professor Neely during the Spring '08 term at USC.

Page1 / 27

realEstimator_mod_1 - Name Value Description seed 0 Random...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online